Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
254
25.7.15 Parallel Programming Characteristics
Figure 25-7. Parallel Programming Timing, Including some General Timing Requirements
Figure 25-8. Parallel Programming Timing, Loading Sequence with Timing Requirements
(1)
Note: 1. The timing requirements shown in Figure 25-7 (i.e., t
DVXH
, t
XHXL
, and t
XLDX
) also apply to loading operation.
XTAL1
PAGEL
WR
Data and Control
(DATA, XA0/1, BS1, BS2)
t
XHXL
t
DVXH
t
BVPH
t
XLWL
t
XLDX
t
PHPL
t
PLBX
t
PLWL
t
BVWL
t
WLBX
t
WLWH
t
WLRL
t
WLRH
RDY/BSY
XTAL1
BS1
PAGEL
DATA
XA0
XA1
t
XLXH
t
PLXH
t
XLPH
Load Address
(Low Byte)
Load Data
(Low Byte)
Load Data
(High Byte)
Load Address
(Low Byte)
Load Data
ADDR0 (Low Byte) ADDR1 (Low Byte)DATA (Low Byte) DATA (High Byte)