Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
236
24.7.2 Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write “00000001” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The content of PCWORD in the Z-register is used to address
the data in the temporary buffer. The temporary buffer will auto-erase after a page write operation or by writing the
RWWSRE bit in SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than one time to
each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM page load operation, all data loaded will be lost.
24.7.3 Performing a Page Write
To execute page write, set up the address in the Z-pointer, write “X0000101” to SPMCSR and execute SPM within four clock
cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page address must be written to PCPAGE. Other bits
in the Z-pointer must be written to zero during this operation.
● Page write to the RWW section: The NRWW section can be read during the page Write.
● Page write to the NRWW section: The CPU is halted during the operation.
24.7.4 Using the SPM Interrupt
If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SELFPRGEN bit in SPMCSR is
cleared. This means that the interrupt can be used instead of polling the SPMCSR register in software. When using the SPM
interrupt, the interrupt vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section
when it is blocked for reading. How to move the interrupts is described in Section 8.9 “Watchdog Timer” on page 44.
24.7.5 Consideration While Updating BLS
Special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11
unprogrammed. An accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates
might be impossible. If it is not necessary to change the boot loader software itself, it is recommended to program the boot
lock bit11 to protect the boot loader software from any internal software changes.
24.7.6 Prevent Reading the RWW Section During Self-Programming
During self-programming (either page erase or page write), the RWW section is always blocked for reading. The user
software itself must prevent that this section is addressed during the self programming operation. The RWWSB in the
SPMCSR will be set as long as the RWW section is busy. During self-programming the interrupt vector table should be
moved to the BLS as described in Section 8.9 “Watchdog Timer” on page 44, or the interrupts must be disabled. Before
addressing the RWW section after the programming is completed, the user software must clear the RWWSB by writing the
RWWSRE. See Section 24.7.12 “Simple Assembly Code Example for a Boot Loader” on page 238 for an example.
24.7.7 Setting the Boot Loader Lock Bits by SPM
To set the boot loader lock bits, write the desired data to R0, write “X0001001” to SPMCSR and execute SPM within four
clock cycles after writing SPMCSR. The only accessible lock bits are the boot lock bits that may prevent the application and
boot loader section from any software update by the MCU.
See Table 24-2 on page 232 and Table 24-3 on page 232 for how the different settings of the boot loader bits affect the flash
access.
If bits 5..2 in R0 are cleared (zero), the corresponding boot lock bit will be programmed if an SPM instruction is executed
within four cycles after BLBSET and SELFPRGEN are set in SPMCSR. The Z-pointer is don’t care during this operation, but
for future compatibility it is recommended to load the Z-pointer with 0x0001 (same as used for reading the lO
ck
bits). For
future compatibility it is also recommended to set bits 7, 6, 1, and 0 in R0 to “1” when writing the lock bits. When
programming the lock bits the entire flash can be read during the operation.
Bit 76543210
R0 1 1 BLB12 BLB11 BLB02 BLB01 1 1