Datasheet

233
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
24.5 “Entering the Boot Loader Program
Entering the boot loader takes place by a jump or call from the application program. This may be initiated by a trigger such
as a command received via USART, or SPI interface. Alternatively, the boot reset fuse can be programmed so that the reset
vector is pointing to the boot flash start address after a reset. In this case, the boot loader is started after a reset. After the
application code is loaded, the program can start executing the application code. Note that the fuses cannot be changed by
the MCU itself. This means that once the boot reset fuse is programmed, the reset vector will always point to the boot loader
reset and the fuse can only be changed through the serial or parallel programming interface.
24.5.1 Store Program Memory Control and Status Register – SPMCSR
The store program memory control and status register contains the control bits needed to control the boot loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the status register is set (one), the SPM ready interrupt will be enabled.
The SPM ready interrupt will be executed as long as the SELFPRGEN bit in the SPMCSR register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a self-programming (page erase or page write) operation to the RWW section is initiated, the RWWSB will be set
(one) by hardware. When the RWWSB bit is set, the RWW section cannot be accessed. The RWWSB bit will be cleared if
the RWWSRE bit is written to one after a self-programming operation is completed. Alternatively the RWWSB bit will
automatically be cleared if a page load operation is initiated.
• Bit 5 – Res: Reserved Bit
This bit is a reserved bit in the Atmel
®
ATmega48/88/168 and always read as zero.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (page erase or page write) to the RWW section, the RWW section is blocked for reading (the RWWSB
will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed
(SELFPRGEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SELFPRGEN, the next SPM
instruction within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled while the flash is
busy with a page erase or a page write (SELFPRGEN is set). If the RWWSRE bit is written while the flash is being loaded,
the flash load operation will abort and the data loaded will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four clock cycles sets boot lock
bits and memory lock bits, according to the data in R0. The data in R1 and the address in the Z-pointer are ignored. The
BLBSET bit will automatically be cleared upon completion of the lock bit set, or if no SPM instruction is executed within four
clock cycles.
An LPM instruction within three cycles after BLBSET and SELFPRGEN are set in the SPMCSR register, will read either the
lock bits or the fuse bits (depending on Z0 in the Z-pointer) into the destination register. See Section 24.7.9 “Reading the
Fuse and Lock Bits from Software” on page 237 for details.
Table 24-4. Boot Reset Fuse
(1)
BOOTRST Reset Address
1 Reset vector = application reset (address 0x0000)
0 Reset vector = boot loader reset (see Table 24-6 on page 240)
Note: 1. “1” means unprogrammed, “0” means programmed
Bit 7 6 5 4 3 2 1 0
SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SELFPRGEN SPMCSR
Read/Write R/W R R R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0