Datasheet

23
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
6. System Clock and Clock Options
6.1 Clock Systems and their Distribution
Figure 6-1 presents the principal clock systems in the AVR
®
and their distribution. All of the clocks need not be active at a
given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different
sleep modes, as described in Section 7. “Power Management and Sleep Modes” on page 33. The clock systems are detailed
below.
Figure 6-1. Clock Distribution
6.1.1 CPU Clock – clk
CPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are
the general purpose register file, the status register and the data memory holding the stack pointer. Halting the CPU clock
inhibits the core from performing general operations and calculations.
6.1.2 I/O Clock – clk
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by
the external interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such
interrupts to be detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried
out asynchronously when clk
I/O
is halted, TWI address recognition in all sleep modes.
6.1.3 Flash Clock – clk
FLASH
The flash clock controls operation of the flash interface. The flash clock is usually active simultaneously with the CPU clock.
Asynchronous
Timer/Counter
Flash and
EEPROM
Timer/Counter
Oscillator
Calibrated RC
Oscillator
Low-frequency
Crystal Oscillator
Crystal
Oscillator
Watchdog
Oscillator
System Clock
Prescaler
General I/O
Modules
AVR Clock
Control Unit
ADC
External Clock
CPU Core
Source clock Watchdog clock
RAM
Reset Logic Watchdog Timer
clk
I/O
clk
ASY
clk
CPU
clk
ADC
clk
FLASH
Clock
Multiplexer