Datasheet
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
220
21.6.4 ADC Control and Status Register B – ADCSRB
• Bit 7, 5:3 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bist must be written to zero when
ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE
is cleared, the ADTS2:0 settings will have no effect. A conversion will be triggered by the rising edge of the selected interrupt
flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on
the trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to free running mode (ADTS[2:0]=0) will
not cause a trigger event, even if the ADC interrupt flag is set
.
21.6.5 Digital Input Disable Register 0 – DIDR0
• Bits 7:6 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bits must be written to zero when
DIDR0 is written.
• Bit 5..0 – ADC5D..ADC0D: ADC5..0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN
register bit will always read as zero when this bit is set. When an analog signal is applied to the ADC5..0 pin and the digital
input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
Note that ADC pins ADC7 and ADC6 do not have digital input buffers, and therefore do not require digital input disable bits.
Bit 76543210
– ACME – – – ADTS2 ADTS1 ADTS0 ADCSRB
Read/Write R R/W R R R R/W R/W R/W
Initial Value00000000
Table 21-5. ADC Auto Trigger Source Selections
ADTS2 ADTS1 ADTS0 Trigger Source
0 0 0 Free running mode
0 0 1 Analog comparator
0 1 0 External interrupt request 0
0 1 1 Timer/Counter0 compare match A
1 0 0 Timer/Counter0 overflow
1 0 1 Timer/Counter1 compare match B
1 1 0 Timer/Counter1 overflow
1 1 1 Timer/Counter1 capture event
Bit 76543210
––ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D DIDR0
Read/Write R R R/W R/W R/W R/W R/W R/W
Initial Value00000000