Datasheet

19
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
• Bit 2 – EEMPE: EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting
EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will
have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles.
See the description of the EEPE bit for an EEPROM write procedure.
• Bit 1 – EEPE: EEPROM Write Enable
The EEPROM write enable signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up,
the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a
logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when
writing the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEPE becomes zero.
2. Wait until SELFPRGEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the flash memory. The software must check that the flash
programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a boot
loader allowing the CPU to program the flash. If the flash is never being updated by the CPU, step 2 can be omitted. See
Section 24. “Boot Loader Support – Read-While-Write Self-Programming, ATmega88 and ATmega168” on page 229 for
details about boot programming.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM master write enable
will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR
or EEDR register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have
the global interrupt flag cleared during all the steps to avoid these problems.
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait
for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction
is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM read enable signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR
register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one
instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles
before the next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible
to read the EEPROM, nor to change the EEAR register.
The calibrated oscillator is used to time the EEPROM accesses. Table 5-2 lists the typical programming time for EEPROM
access from the CPU.
Table 5-2. EEPROM Programming Time
Symbol Number of Calibrated RC Oscillator Cycles Typical Programming Time
EEPROM write (from
CPU)
26,368 3.3ms