Datasheet

185
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
19.6.6 TWI (Slave) Address Mask Register – TWAMR
• Bits 7..1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit salve address mask. Each of the bits in TWAMR can mask (disable) the
corresponding address bits in the TWI address register (TWAR). If the mask bit is set to one then the address match logic
ignores the compare between the incoming address bit and the corresponding bit in TWAR. Figure 19-10 shown the address
match logic in detail.
Figure 19-10. TWI Address Match Logic, Block Diagram
• Bit 0 – Res: Reserved Bit
This bit is an unused bit in the Atmel
®
ATmega48/88/168, and will always read as zero.
19.7 Using the TWI
The AVR
®
TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or
transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other
operations during a TWI byte transfer. Note that the TWI interrupt enable (TWIE) bit in TWCR together with the global
interrupt enable bit in SREG allow the application to decide whether or not assertion of the TWINT flag should generate an
interrupt request. If the TWIE bit is cleared, the application must poll the TWINT flag in order to detect actions on the TWI
bus.
When the TWINT flag is asserted, the TWI has finished an operation and awaits application response. In this case, the TWI
status register (TWSR) contains a value indicating the current state of the TWI bus. The application software can then
decide how the TWI should behave in the next TWI bus cycle by manipulating the TWCR and TWDR registers.
Figure 19-11 on page 186 is a simple example of how the application can interface to the TWI hardware. In this example, a
Master wishes to transmit a single data byte to a slave. This description is quite abstract, a more detailed explanation follows
later in this section. A simple code example implementing the desired behavior is also presented.
Bit 76543210
TWAM[6:0] – TWAMR
Read/Write R/W R/W R/W R/W R/W R/W R/W R
Initial Value00000000
TWAR0
Address
Match
TWAMR0
Address Bit Comparator 6 to 1
Address Bit Comparator 0
Address
Bit 0