Datasheet

181
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
19.5.2 Bit Rate Generator Unit
This unit controls the period of SCL when operating in a master mode. The SCL period is controlled by settings in the TWI bit
rate register (TWBR) and the prescaler bits in the TWI status register (TWSR). Slave operation does not depend on bit rate
or prescaler settings, but the CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency.
Note that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period. The SCL frequency is
generated according to the following equation:
● TWBR = value of the TWI bit rate register.
● Prescaler value = value of the prescaler, see Table 19-2 on page 184.
Note: TWBR should be 10 or higher if the TWI operates in master mode. If TWBR is lower than 10, the master may
produce an incorrect output on SDA and SCL for the reminder of the byte. The problem occurs when operating
the TWI in master mode, sending start + SLA + R/W to a slave (a slave does not need to be connected to the
bus for the condition to happen).
19.5.3 Bus Interface Unit
This unit contains the data and address shift register (TWDR), a START/STOP controller and arbitration detection hardware.
The TWDR contains the address or data bytes to be transmitted, or the address or data bytes received. In addition to the
8-bit TWDR, the bus interface unit also contains a register containing the (N)ACK bit to be transmitted or received. This
(N)ACK register is not directly accessible by the application software. However, when receiving, it can be set or cleared by
manipulating the TWI control register (TWCR). When in transmitter mode, the value of the received (N)ACK bit can be
determined by the value in the TWSR.
The START/STOP controller is responsible for generation and detection of START, REPEATED START, and STOP
conditions. The START/STOP controller is able to detect START and STOP conditions even when the AVR MCU is in one of
the sleep modes, enabling the MCU to wake up if addressed by a master.
If the TWI has initiated a transmission as master, the arbitration detection hardware continuously monitors the transmission
trying to determine if arbitration is in process. If the TWI has lost an arbitration, the control unit is informed. Correct action
can then be taken and appropriate status codes generated.
19.5.4 Address Match Unit
The address match unit checks if received address bytes match the seven-bit address in the TWI address register (TWAR).
If the TWI general call recognition enable (TWGCE) bit in the TWAR is written to one, all incoming address bits will also be
compared against the general call address. Upon an address match, the control unit is informed, allowing correct action to
be taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR. The address match unit is
able to compare addresses even when the AVR
®
MCU is in sleep mode, enabling the MCU to wake up if addressed by a
master. If another interrupt (e.g., INT0) occurs during TWI power-down address match and wakes up the CPU, the TWI
aborts operation and return to it’s idle state. If this cause any problems, ensure that TWI address match is the only enabled
interrupt when entering power-down.
19.5.5 Control Unit
The control unit monitors the TWI bus and generates responses corresponding to settings in the TWI control register
(TWCR). When an event requiring the attention of the application occurs on the TWI bus, the TWI interrupt flag (TWINT) is
asserted. In the next clock cycle, the TWI status register (TWSR) is updated with a status code identifying the event. The
TWSR only contains relevant status information when the TWI interrupt flag is asserted. At all other times, the TWSR
contains a special status code indicating that no relevant status information is available. As long as the TWINT flag is set, the
SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to
continue.
SCL frequency
CPU Clock frequency
16 2(TWBR) PrescalerValue()⋅+
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