Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
180
Note that arbitration is not allowed between:
● A REPEATED START condition and a data bit.
● A STOP condition and a data bit.
● A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in
multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All
transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined.
19.5 Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 19-9. All registers drawn in a thick line are
accessible through the AVR
®
data bus.
Figure 19-9. Overview of the TWI Module
19.5.1 SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to
conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50ns. Note
that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins,
as explained in the I/O port section. The internal pull-ups can in some systems eliminate the need for external ones.
START/ STOP
Control
Spike
Filter
Slew-rate
Control
Address/ Data Shift
Register (TWDR)
Arbitration detection
Spike Suppression
Bit Rate Register
(TWBR)
Prescaler
Ack
Bus Interface Unit
SCL
Spike
Filter
Slew-rate
Control
SDA
Bit Rate Generator
Address Register
(TWAR)
Address Comparator
Address Match Unit
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status control
Control Unit
TWI Unit