Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
178
Figure 19-5. Data Packet Format
19.3.5 Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An
empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line
can be used to implement handshaking between the master and the slave. The slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the master is too fast for the slave, or the slave needs
extra time for processing between the data transmissions. The slave extending the SCL low period will not affect the SCL
high period, which is determined by the master. As a consequence, the slave can reduce the TWI data transfer speed by
prolonging the SCL duty cycle.
Figure 19-6 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and
the STOP condition, depending on the software protocol implemented by the application software.
Figure 19-6. Typical Data Transmission
19.4 Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that
transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems
arise in multi-master systems:
● An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters
should cease transmission when they discover that they have lost the selection process. This selection process is
called arbitration. When a contending master discovers that it has lost the arbitration process, it should immediately
switch to slave mode to check whether it is being addressed by the winning master. The fact that multiple masters
have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on
the bus must not be corrupted.
● Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks
from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration
process.
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
Data MSB Data LSB ACK
12 7
Data Byte
STOP, REPEATED
START or next
Data Byte
SLA + R/W
89
SDA
SCL
STOPSTART SLA + R/W Data Byte
Addr MSB Addr LSB Data MSB Data LSB ACKR/W ACK
12 789
12 789