Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
172
18.5.1 Transmitter and Receiver Flags and Interrupts
The RXCn, TXCn, and UDREn flags and corresponding interrupts in USART in MSPIM mode are identical in function to the
normal USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as
zero.
18.5.2 Disabling the Transmitter or Receiver
The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation.
18.6 USART MSPIM Register Description
The following section describes the registers used for SPI operation using the USART.
18.6.1 USART MSPIM I/O Data Register - UDRn
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to normal USART operation.
See Section 17.9.1 “USART I/O Data Register n– UDRn” on page 161
18.6.2 USART MSPIM Control and Status Register n A - UCSRnA
• Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does
not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and consequently the RXCn bit will
become zero. The RXCn flag can be used to generate a receive complete interrupt (see description of the RXCIEn bit).
• Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently
present in the transmit buffer (UDRn). The TXCn flag bit is automatically cleared when a transmit complete interrupt is
executed, or it can be cleared by writing a one to its bit location. The TXCn flag can generate a transmit complete interrupt
(see description of the TXCIEn bit).
• Bit 5 - UDREn: USART Data Register Empty
The UDREn flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty,
and therefore ready to be written. The UDREn flag can generate a data register empty interrupt (see description of the
UDRIE bit). UDREn is set after a reset to indicate that the transmitter is ready.
• Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices, these bits must be written
to zero when UCSRnA is written.
18.6.3 USART MSPIM Control and Status Register n B - UCSRnB
• Bit 7 - RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn flag. A USART receive complete interrupt will be generated only if the
RXCIEn bit is written to one, the global interrupt flag in SREG is written to one and the RXCn bit in UCSRnA is set.
Bit 7 6 5 4 3 2 1 0
RXCn TXCn UDREn - - - - - UCSRnA
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 1 1 0
Bit 7 6543210
RXCIEn TXCIEn UDRIE RXENn TXENn - - - UCSRnB
Read/Write R/W R/W R/W R/W R/W R R R
Initial Value 0 0 0 0 0 1 1 0