Datasheet

17
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM access is
performed in two clk
CPU
cycles as described in Figure 5-4.
Figure 5-4. On-chip Data SRAM Access Cycles
5.3 EEPROM Data Memory
The Atmel ATmega48/88/168 contains 256/512/512 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase
cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM address
registers, the EEPROM data register, and the EEPROM control register.
Section 25. “Memory Programming” on page 242 contains a detailed description on EEPROM programming in SPI or
parallel programming mode.
5.3.1 EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 5-2 on page 19. A self-timing function, however, lets the user
software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some
precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section 5.3.5 “Preventing EEPROM Corruption” on page 21 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the
EEPROM control register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the
EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
5.3.2 The EEPROM Address Register – EEARH and EEARL
clk
CPU
T1
Data
Data
RD
WR
Address validCompute Address
Next Instruction
Write
Read
Memory Access Instruction
Address
T2 T3
Bit 151413121110 9 8
–––––––EEAR8EEARH
EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL
76543210
Read/Write RRRRRRRR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value0000000X
XXXXXXXX