Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
168
18. USART in SPI Mode
The universal synchronous and asynchronous serial receiver and transmitter (USART) can be set to a master SPI compliant
mode of operation. The master SPI mode (MSPIM) has the following features:
● Full duplex, three-wire synchronous data transfer
● Master operation
● Supports all four SPI modes of operation (mode 0, 1, 2, and 3)
● LSB first or MSB first data transfer (configurable data order)
● Queued operation (double buffered)
● High resolution baud rate generator
● High speed operation (fXCKmax = fCK/2)
● Flexible interrupt generation
18.1 Overview
Setting both UMSELn1:0 bits to one enables the USART in MSPIM logic. In this mode of operation the SPI master control
logic takes direct control over the USART resources. These resources include the transmitter and receiver shift register and
buffers, and the baud rate generator. The parity generator and checker, the data and clock recovery logic, and the RX and
TX control logic is disabled. The USART RX and TX control logic is replaced by a common SPI transfer control logic.
However, the pin control logic and interrupt generation logic is identical in both modes of operation.
The I/O register locations are the same in both modes. However, some of the functionality of the control registers changes
when using MSPIM.
18.2 Clock Generation
The clock generation logic generates the base clock for the transmitter and receiver. For USART MSPIM mode of operation
only internal clock generation (i.e. master operation) is supported. The data direction register for the XCKn pin (DDR_XCKn)
must therefore be set to one (i.e. as output) for the USART in MSPIM to operate correctly. Preferably the DDR_XCKn should
be set up before the USART in MSPIM is enabled (i.e. TXENn and RXENn bit set to one).
The internal clock generation used in MSPIM mode is identical to the USART synchronous master mode. The baud rate or
UBRRn setting can therefore be calculated using the same equations, see Table 18-1.
BAUD Baud rate (in bits per second, bps)
f
OSC
System oscillator clock frequency
UBRRn Contents of the UBRRnH and UBRRnL registers, (0-4095)
Table 18-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Equation for Calculating Baud Rate
(1)
Equation for Calculating UBRRn Value
Synchronous master mode
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
f
OSC
2 UBRRn 1+()
--------------------------------------
=
UBRRn
f
OSC
2BAUD
--------------------
1–=