Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
164
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the transmitter. The receiver ignores this setting.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits (character size) in a frame the
receiver and transmitter use.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets
the relationship between data output change and data input sample, and the synchronous clock (XCKn).
17.9.5 USART Baud Rate Registers – UBRRnL and UBRRnH
Table 17-6. USBS Bit Settings
USBSn Stop Bit(s)
0 1-bit
1 2-bit
Table 17-7. UCSZn Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
0 0 0 5-bit
0 0 1 6-bit
0 1 0 7-bit
0 1 1 8-bit
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 9-bit
Table 17-8. UCPOLn Bit Settings
UCPOLn Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin)
0 Rising XCKn edge Falling XCKn edge
1 Falling XCKn edge Rising XCKn edge
Bit 151413121110 9 8
–––– UBRRn[11:8] UBRRnH
UBRRn[7:0] UBRRnL
76543210
Read/Write
RRRRR/WR/WR/WR/W
R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value
00000000
00000000