Datasheet

149
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
Table 17-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRRn value for each
mode of operation using an internally generated clock source.
BAUD Baud rate (in bits per second, bps)
f
OSC
System oscillator clock frequency
UBRRn Contents of the UBRRnH and UBRRnL registers, (0-4095)
Some examples of UBRRn values for some system clock frequencies are found in Table 17-9 on page 165.
17.2.2 Double Speed Operation (U2Xn)
The transfer rate can be doubled by setting the U2Xn bit in UCSRnA. Setting this bit only has effect for the asynchronous
operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for
asynchronous communication. Note however that the receiver will in this case only use half the number of samples (reduced
from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are
required when this mode is used. For the transmitter, there are no downsides.
17.2.3 External Clock
External clocking is used by the synchronous slave modes of operation. The description in this section refers to
Figure 17-2 on page 148 for details.
External clock input from the XCKn pin is sampled by a synchronization register to minimize the chance of meta-stability.
The output from the synchronization register must then pass through an edge detector before it can be used by the
transmitter and receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCKn
clock frequency is limited by the following equation:
Note that f
osc
depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid
possible loss of data due to frequency variations.
17.2.4 Synchronous Clock Operation
When synchronous mode is used (UMSELn = 1), the XCKn pin will be used as either clock input (slave) or clock output
(master). The dependency between the clock edges and data sampling or data change is the same. The basic principle is
that data input (on RxDn) is sampled at the opposite XCKn clock edge of the edge the data output (TxDn) is changed.
Table 17-1. Equations for Calculating Baud Rate Register Setting
Operating Mode Equation for Calculating Baud Rate
(1)
Equation for Calculating UBRRn Value
Asynchronous normal mode
(U2Xn = 0)
Asynchronous double speed
mode (U2Xn = 1)
Synchronous master mode
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps)
BAUD
f
OSC
16 UBRRn 1+()
-----------------------------------------
=
UBRRn
f
OSC
16BAUD
-----------------------
1–=
BAUD
f
OSC
8 UBRRn 1+()
--------------------------------------
=
UBRRn
f
OSC
8BAUD
--------------------
1–=
BAUD
f
OSC
2 UBRRn 1+()
--------------------------------------
=
UBRRn
f
OSC
2BAUD
--------------------
1–=
f
XCK
f
OSC
4
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