Datasheet

147
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
17.1 Overview
A simplified block diagram of the USART Transmitter is shown in Figure 17-1. CPU accessible I/O Registers and I/O pins are
shown in bold.
Figure 17-1. USART Block Diagram
(1)
Note: 1. Refer to Figure 1-1 on page 3 and Table 10-9 on page 69 for USART0 pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): clock generator,
transmitter and receiver. Control registers are shared by all units. The clock generation logic consists of synchronization
logic for external clock input used by synchronous slave operation, and the baud rate generator. The XCKn (transfer clock)
pin is only used by synchronous transfer mode. The transmitter consists of a single write buffer, a serial shift register, parity
generator and control logic for handling different serial frame formats. The write buffer allows a continuous transfer of data
without any delay between frames. The receiver is the most complex part of the USART module due to its clock and data
recovery units. The recovery units are used for asynchronous data reception. In addition to the recovery units, the receiver
includes a parity checker, control logic, a shift register and a two level receive buffer (UDRn). The receiver supports the
same frame formats as the transmitter, and can detect frame error, data overrun and parity errors.
Transmit Shift Register
Receive Shift Register
Data
Recoverc
Clock
Recoverc
Parity
Checker
Parity
Generator
Pin
Control
TX
Control
Pin
Control
Pin
Control
RX
Control
UDRn (Transmit)
Transmitter
Clock Generator
Receiver
UCSRnA UCSRnCUCSRnB
Sync Logic
OSC
UDRn (Receive)
DATA BUS
Baud Rate Generator
UBRRn [H:L]
XCKn
RxDn
TxDn