Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
144
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the Atmel
®
ATmega48/88/168 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK frequency) will be doubled when the SPI is in master mode
(see Table 16-4 on page 143). This means that the minimum SCK period will be two CPU clock periods. When the SPI is
configured as Slave, the SPI is only guaranteed to work at f
osc
/4 or lower.
The SPI interface on the Atmel ATmega48/88/168 is also used for program memory and EEPROM downloading or
uploading. See Section 25.8 “Serial Downloading” on page 256 for serial programming and verification.
16.1.5 SPI Data Register – SPDR
The SPI data register is a read/write register used for data transfer between the register file and the SPI shift register. Writing
to the register initiates data transmission. Reading the register causes the shift register receive buffer to be read.
16.2 Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits
CPHA and CPOL. The SPI data transfer formats are shown in Figure 16-3 on page 145 and Figure 16-4 on page 145. Data
bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize.
This is clearly seen by summarizing Figure 16-2 on page 142 and Table 16-3 on page 143, as done below.
Bit 76543210
MSB LSB SPDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial ValueXXXXXXXXUndefined
Table 16-5. CPOL Functionality
Leading Edge Trailing eDge SPI Mode
CPOL=0, CPHA=0 Sample (rising) Setup (falling) 0
CPOL=0, CPHA=1 Setup (rising) Sample (falling) 1
CPOL=1, CPHA=0 Sample (falling) Setup (rising) 2
CPOL=1, CPHA=1 Setup (falling) Sample (rising) 3