Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
142
16.1.2 Master Mode
When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin.
If SS
is configured as an output, the pin is a general output pin which does not affect the SPI system. Typically, the pin will be
driving the SS
pin of the SPI slave.
If SS is configured as an input, it must be held high to ensure master SPI operation. If the SS pin is driven low by peripheral
circuitry when the SPI is configured as a master with the SS
pin defined as an input, the SPI system interprets this as
another master selecting the SPI as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the
following actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave,
the MOSI and SCK pins become inputs.
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set, the interrupt routine
will be executed.
Thus, when interrupt-driven SPI transmission is used in master mode, and there exists a possibility that SS
is driven low, the
interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared by a slave select, it must be set
by the user to re-enable SPI master mode.
16.1.3 SPI Control Register – SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the if the global interrupt enable bit
in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects master SPI mode when written to one, and slave SPI mode when written logic zero. If SS
is configured as an
input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have
to set MSTR to re-enable SPI master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to
Figure 16-3 on page 145 and Figure 16-4 on page 145 for an example. The CPOL functionality is summarized below:
Bit 76543210
SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000
Table 16-2. CPOL Functionality
CPOL Leading Edge Trailing Edge
0 Rising Falling
1 Falling Rising