Datasheet

139
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
The interconnection between master and slave CPUs with SPI is shown in Figure 16-2. The system consists of two shift
registers, and a master clock generator. The SPI master initiates the communication cycle when pulling low the slave select
SS
pin of the desired slave. Master and slave prepare the data to be sent in their respective shift registers, and the master
generates the required clock pulses on the SCK line to interchange data. Data is always shifted from master to slave on the
master out – slave In, MOSI, line, and from slave to master on the master In – slave out, MISO, line. After each data packet,
the master will synchronize the slave by pulling high the slave select, SS
, line.
When configured as a master, the SPI interface has no automatic control of the SS
line. This must be handled by user
software before communication can start. When this is done, writing a byte to the SPI data register starts the SPI clock
generator, and the hardware shifts the eight bits into the slave. After shifting one byte, the SPI clock generator stops, setting
the end of transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is
requested. The master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high
the slave select, SS
line. The last incoming byte will be kept in the buffer register for later use.
When configured as a slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high.
In this state, software may update the contents of the SPI data register, SPDR, but the data will not be shifted out by
incoming clock pulses on the SCK pin until the SS
pin is driven low. As one byte has been completely shifted, the end of
transmission flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR register is set, an interrupt is requested. The
slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be
kept in the buffer register for later use.
Figure 16-2. SPI Master-slave Interconnection
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to
be transmitted cannot be written to the SPI data register before the entire shift cycle is completed. When receiving data,
however, a received character must be read from the SPI data register before the next character has been completely
shifted in. Otherwise, the first byte is lost.
In SPI slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock
signal, the frequency of the SPI clock should never exceed f
osc
/4.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to
Table 16-1 on page 139. For more details on automatic port overrides, refer to Section 10.3 “Alternate Port Functions” on
page 62.
Table 16-1. SPI Pin Overrides
(1)
Pin Direction, Master SPI Direction, Slave SPI
MOSI User defined Input
MISO Input User defined
SCK User defined Input
SS User defined Input
Note: 1. See Section 10.3.2 “Alternate Functions of Port B” on page 64 for a detailed description of how to define the
direction of the user defined SPI pins.
LSBSLAVEMSB
8 Bit Shift Register
LSB
Shift
Enable
MASTERMSB
SS
SCK
SS
SCK
MOSIMOSI
MISOMISO
8 Bit Shift Register
SPI
Clock Generator