Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
136
• Bit 0 – TCR2BUB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2B is written, this bit becomes set. When TCCR2B has been
updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2B
is ready to be updated with a new value.
If a write is performed to any of the five Timer/Counter2 registers while its update busy flag is set, the updated value might
get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are different. When reading TCNT2, the
actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage
register is read.
15.10 Timer/Counter Prescaler
Figure 15-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
T2S
. clk
T2S
is by default connected to the main system I/O clock clk
IO
. By
setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of
Timer/Counter2 as a real time counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from port C. A
crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for
Timer/Counter2. The oscillator is optimized for use with a 32.768kHz crystal. Applying an external clock source to TOSC1 is
not recommended.
For Timer/Counter2, the possible prescaled selections are: clk
T2S
/8, clk
T2S
/32, clk
T2S
/64, clk
T2S
/128, clk
T2S
/256, and
clk
T2S
/1024. Additionally, clk
T2S
as well as 0 (stop) may be selected. Setting the PSRASY bit in GTCCR resets the prescaler.
This allows the user to operate with a predictable prescaler.
Timer/Counter2 Clock Source
clk
T2
clk
T2S
/8
clk
T2S
/32
clk
T2S
/64
clk
T2S
/128
clk
T2S
/256
clk
T2S
/1024
clk
I/O
TOSC1
AS2
PSRASY
clk
T2S
10-bit T/C Prescaler
0
Clear
CS20
CS21
CS22