Datasheet

133
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
15.8.6 Timer/Counter2 Interrupt Mask Register – TIMSK2
• Bit 2 – OCIE2B: Timer/Counter2 Output Compare Match B Interrupt Enable
When the OCIE2B bit is written to one and the I-bit in the status register is set (one), the Timer/Counter2 compare match B
interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the
OCF2B bit is set in the Timer/Counter 2 interrupt flag register – TIFR2.
• Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable
When the OCIE2A bit is written to one and the I-bit in the status register is set (one), the Timer/Counter2 compare match A
interrupt is enabled. The corresponding interrupt is executed if a compare match in Timer/Counter2 occurs, i.e., when the
OCF2A bit is set in the Timer/Counter 2 interrupt flag register – TIFR2.
• Bit 0 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the status register is set (one), the Timer/Counter2 overflow interrupt is
enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, i.e., when the TOV2 bit is set in
the Timer/Counter2 interrupt flag register – TIFR2.
15.8.7 Timer/Counter2 Interrupt Flag Register – TIFR2
• Bit 2 – OCF2B: Output Compare Flag 2 B
The OCF2B bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2B – output
compare register2. OCF2B is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF2B is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2B (Timer/Counter2 compare
match interrupt enable), and OCF2B are set (one), the Timer/Counter2 compare match interrupt is executed.
• Bit 1 – OCF2A: Output Compare Flag 2 A
The OCF2A bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2A – output
compare register2. OCF2A is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, OCF2A is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2A (Timer/Counter2 compare
match interrupt enable), and OCF2A are set (one), the Timer/Counter2 compare match interrupt is executed.
• Bit 0 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the
SREG I-bit, TOIE2A (Timer/Counter2 overflow interrupt enable), and TOV2 are set (one), the Timer/Counter2 overflow
interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
Bit 76543 2 1 0
– – – – – OCIE2B OCIE2A TOIE2 TIMSK2
Read/WriteRRRRR R/WR/WR/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
–––––OCF2BOCF2ATOV2TIFR2
Read/Write RRRRRR/WR/WR/W
Initial Value00000000