Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
130
• Bits 5:4 – COM2B1:0: Compare Match Output B Mode
These bits control the output compare pin (OC2B) behavior. If one or both of the COM2B1:0 bits are set, the OC2B output
overrides the normal port functionality of the I/O pin it is connected to. However, note that the data direction register (DDR)
bit corresponding to the OC2B pin must be set in order to enable the output driver.
When OC2B is connected to the pin, the function of the COM2B1:0 bits depends on the WGM22:0 bit setting. Table 15-5
shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to a normal or CTC mode (non-PWM).
Table 15-6 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to fast PWM mode.
Table 15-7 shows the COM2B1:0 bit functionality when the WGM22:0 bits are set to phase correct PWM mode.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the Atmel
®
ATmega48/88/168 and will always read as zero.
• Bits 1:0 – WGM21:0: Waveform Generation Mode
Combined with the WGM22 bit found in the TCCR2B register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 15-8. Modes of
operation supported by the Timer/Counter unit are: normal mode (counter), clear timer on compare match (CTC) mode, and
two types of pulse width modulation (PWM) modes (see Section 15.6 “Modes of Operation” on page 123).
Table 15-5. Compare Output Mode, non-PWM Mode
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Toggle OC2B on compare match
1 0 Clear OC2B on compare match
1 1 Set OC2B on compare match
Table 15-6. Compare Output Mode, Fast PWM Mode
(1)
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Reserved
1 0 Clear OC2B on compare match, set OC2B at TOP
1 1 Set OC2B on compare match, clear OC2B at TOP
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 15.6.4 “Phase Correct PWM Mode” on page 126 for
more details.
Table 15-7. Compare Output Mode, Phase Correct PWM Mode
(1)
COM2B1 COM2B0 Description
0 0 Normal port operation, OC2B disconnected.
0 1 Reserved
1 0
Clear OC2B on compare match when up-counting. Set OC2B on compare match when
down-counting.
1 1
Set OC2B on compare match when up-counting. Clear OC2B on compare match when
down-counting.
Note: 1. A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the compare match is
ignored, but the set or clear is done at TOP. See Section 15.6.4 “Phase Correct PWM Mode” on page 126 for
more details.