Datasheet
127
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2x pin. Setting the
COM2x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM2x1:0 to three. TOP is defined as 0xFF when WGM2:0 = 3, and OCR2A when MGM2:0 = 7
(See Table 15-4 on page 129). The actual OC2x value will only be visible on the port pin if the data direction for the port pin
is set as output. The PWM waveform is generated by clearing (or setting) the OC2x register at the compare match between
OCR2x and TCNT2 when the counter increments, and setting (or clearing) the OC2x register at compare match between
OCR2x and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A register represent special cases when generating a PWM waveform output in the phase
correct PWM mode. If the OCR2A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the
output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
At the very start of period 2 in Figure 15-7 on page 126 OCnx has a transition from high to low even though there is no
compare match. The point of this transition is to guarantee symmetry around BOTTOM. There are two cases that give a
transition without compare match.
● OCR2A changes its value from MAX, like in Figure 15-7 on page 126. When the OCR2A value is MAX the OCn pin
value is the same as the result of a down-counting compare match. To ensure symmetry around BOTTOM the OCn
value at MAX must correspond to the result of an up-counting compare match.
● The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the compare match
and hence the OCn change that would have happened on the way up.
15.7 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
T2
) is therefore shown as a clock
enable signal. In asynchronous mode, clk
I/O
should be replaced by the Timer/Counter oscillator clock. The figures include
information on when interrupt flags are set. Figure 15-8 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 15-8. Timer/Counter Timing Diagram, no Prescaling
f
OCnxPCPWM
f
clk_I/O
N 510⋅
-----------------
=
MAX - 1
clk
I/O
(clk
I/O
/1)
TCNTn
TOVn
clk
Tn
MAX BOTTOM BOTTOM + 1