Datasheet

121
ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
Signal description (internal signals):
count Increment or decrement TCNT2 by 1.
direction Selects between increment and decrement.
clear Clear TCNT2 (set all bits to zero).
clk
Tn
Timer/Counter clock, referred to as clk
T2
in the following.
top Signalizes that TCNT2 has reached maximum value.
bottom Signalizes that TCNT2 has reached minimum value (zero).
Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk
T2
).
clk
T2
can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock
source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of
whether clk
T2
is present or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter control
register (TCCR2A) and the WGM22 located in the Timer/Counter control register B (TCCR2B). There are close connections
between how the counter behaves (counts) and how waveforms are generated on the output compare outputs OC2A and
OC2B. For more details about advanced counting sequences and waveform generation, see Section 15.6 “Modes of
Operation” on page 123.
The Timer/Counter overflow flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can
be used for generating a CPU interrupt.
15.4 Output Compare Unit
The 8-bit comparator continuously compares TCNT2 with the output compare register (OCR2A and OCR2B). Whenever
TCNT2 equals OCR2A or OCR2B, the comparator signals a match. A match will set the output compare flag (OCF2A or
OCF2B) at the next timer clock cycle. If the corresponding interrupt is enabled, the output compare flag generates an output
compare interrupt. The output compare flag is automatically cleared when the interrupt is executed. Alternatively, the output
compare flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the
match signal to generate an output according to operating mode set by the WGM22:0 bits and compare output mode
(COM2x1:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the
extreme values in some modes of operation (Section 15.6 “Modes of Operation” on page 123).
Figure 15-3 shows a block diagram of the output compare unit.
Figure 15-3. Output Compare Unit, Block Diagram
OCFnx (Int. Req.)
= (8-bit Comparator)
OCRnx
Waveform Generator
TCNTn
OCnx
top
bottom
FOCn
WGMn1:0 COMnX1:0
DATA BUS