Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
114
Table 14-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast PWM mode.
Table 14-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and
frequency correct, PWM mode.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B register, these bits control the counting sequence of the counter, the
source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 14-5. Modes of
operation supported by the Timer/Counter unit are: Normal mode (counter), clear timer on compare match (CTC) mode, and
three types of pulse width modulation (PWM) modes. (See Section 14.8 “Modes of Operation” on page 105).
Table 14-3. Compare Output Mode, Fast PWM
(1)
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1
WGM13:0 = 14 or 15: Toggle OC1A on compare match, OC1B
disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
1 0 Clear OC1A/OC1B on compare match, set OC1A/OC1B at TOP
1 1 Set OC1A/OC1B on compare match, clear OC1A/OC1B at TOP
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the
compare match is ignored, but the set or clear is done at TOP.
See Section 14.8.3 “Fast PWM Mode” on page 106 for more details.
Table 14-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM
(1)
COM1A1/COM1B1 COM1A0/COM1B0 Description
0 0 Normal port operation, OC1A/OC1B disconnected.
0 1
WGM13:0 = 8, 9, 10 or 11: Toggle OC1A on compare match,
OC1B disconnected (normal port operation). For all other WGM1
settings, normal port operation, OC1A/OC1B disconnected.
1 0
Clear OC1A/OC1B on compare match when up-counting.
Set OC1A/OC1B on compare match when downcounting.
1 1
Set OC1A/OC1B on compare match when up-counting.
Clear OC1A/OC1B on compare match when downcounting.
Note: 1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set.
See Section 14.8.4 “Phase Correct PWM Mode” on page 108 for more details.
Table 14-5. Waveform Generation Mode Bit Description
(1)
Mode WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation TOP
Update of
OCR1x at
TOV1 Flag
Set on
0 0 0 0 0 Normal 0xFFFF Immediate MAX
1 0 0 0 1 PWM, phase correct, 8-bit 0x00FF TOP BOTTOM
2 0 0 1 0 PWM, phase correct, 9-bit 0x01FF TOP BOTTOM
3 0 0 1 1 PWM, phase correct, 10-bit 0x03FF TOP BOTTOM
4 0 1 0 0 CTC OCR1A Immediate MAX
5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP
6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP
7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP
8 1 0 0 0
PWM, phase and frequency
correct
ICR1 BOTTOM BOTTOM
Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the
functionality and location of these bits are compatible with previous versions of the timer.