Datasheet

ATmega48/88/168 Automotive [DATASHEET]
7530K–AVR–07/14
112
Figure 14-11 shows the same timing data, but with the prescaler enabled.
Figure 14-11.Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
clk_I/O
/8)
Figure 14-12 shows the count sequence close to TOP in various modes. When using phase and frequency correct PWM
mode the OCR1x register is updated at BOTTOM. The timing diagrams will be the same, but TOP should be replaced by
BOTTOM, TOP-1 by BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM.
Figure 14-12.Timer/Counter Timing Diagram, no Prescaling
OCRnx - 1
clk
I/O
(clk
I/O
/8)
TCNTn
OCRnx
OCFnx
clk
Tn
OCRnx OCRnx + 1
OCRnx Value
OCRnx + 2
TOP - 1
clk
I/O
(clk
I/O
/1)
TCNTn
(CTC and FPWM)
OCRnx
(Update at TOP)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn
(if used as TOP)
clk
Tn
TOP
Old OCRnx Value New OCRnx Value
BOTTOM BOTTOM + 1
TOP - 1 TOP TOP -1 TOP -2