Datasheet

39
7766E–AVR–04/10
ATmega16U4/ATmega32U4
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
6.10 PLL
The PLL is used to generate internal high frequency (up to 96MHz) clock for USB interface
and/or High Speed Timer module, the PLL input is supplied from an external low-frequency
clock (the crystal oscillator or external clock input pin from XTAL1).
6.10.1 Internal PLL
The internal PLL in ATmega16U4/ATmega32U4 generates a clock frequency between 32MHz
and 96 MHz from nominally 8MHz input.
The source of the 8MHz PLL input clock is the output of the internal PLL clock prescaler that
generates the 8MHz from the clock source multiplexer output (See Section 6.10.2 for PLL inter-
face). The PLL prescaler allows a direct connection (8MHz oscillator) or a divide-by-2 stage for a
16MHz clock input.
The PLL output signal enters the PLL Postcaler stage before being distributed to the USB and
High Speed Timer modules. Each of these modules can choose an independent division ratio.
Table 6-10. Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 128
1000 256
1001 Reserved
1010 Reserved
1011 Reserved
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved