Datasheet

253
7766E–AVR–04/10
ATmega16U4/ATmega32U4
21. USB controller
21.1 Features
• Supports full-speed and low-speed Device role
• Complies with USB Specification v2.0
• Supports ping-pong mode (dual bank)
• 832 bytes of DPRAM:
– 1 endpoint 64 bytes max (default control endpoint)
– 1 endpoints of 256 bytes max, (one or two banks)
– 5 endpoints of 64 bytes max, (one or two banks)
• Crystal-less operation for low-speed mode
21.2 Block Diagram
The USB controller provides the hardware to interface a USB link to a data flow stored in a dou-
ble port memory (DPRAM).
The USB controller requires a 48 MHz ±0.25% reference clock (for Full-Speed operation), which
is the output of an internal PLL. The on-chip PLL generates the internal high frequency (48 MHz)
clock for USB interface. The PLL clock input can be configured to use external low-power crystal
oscillator, external source clock or internal RC (see Section “Crystal-less operation”, page 256).
The 48MHz clock is used to generate a 12 MHz Full-speed (or 1.5 MHz Low-Speed) bit clock
from the received USB differential data and to transmit data according to full or low speed USB
device tolerance. Clock recovery is done by a Digital Phase Locked Loop (DPLL) block, which is
compliant with the jitter specification of the USB bus.
To comply with the USB Electrical specification, USB buffers (D+ or D-) should be powered
within the 3.0 to 3.6V range. As ATmega16U4/ATmega32U4 can be powered up to 5.5V, an
internal regulator provides the USB buffers power supply.
Figure 21-1. USB controller Block Diagram overview
CPU
USB Regulator
USB
Interface
PLL
clk
8MHz
clk
48MHz
PLL clock
Prescaler
On-Chip
USB DPRAM
DPLL
Clock
Recovery
UCAP
D-
D+
VBUS
UVCC AVCC
Div-by-2
&
XT1
Clock Mux
IntRC