Datasheet

2
7799ES–AVR–09/2012
ATmega8U2/16U2/32U2
1. Pin Configurations
Figure 1-1. Pinout
Note: The large center pad underneath the QFN package should be soldered to ground on the board to
ensure good mechanical stability.
1.1 Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
UVCC
QFN32
(PCINT11 / AIN2 ) PC2
(OC.0B / INT0) PD0
VCC
XTAL1
(INT5/ AIN3) PD4
(TXD1 / INT3) PD3
(XCK / AIN4 / PCINT12) PD5
PB3 (PDO / MISO / PCINT3)
GND
(PC0) XTAL2
UGND
PB4 (T1 / PCINT4)
28 27 26
1
2
3
4
5
6
7
24
23
22
21
20
19
18
1211109131415
(AIN0 / INT1) PD1
8
16
17
PB6 (PCINT6)
D- D+
2529303132
PB7 (PCINT7 / OC.0A / OC.1C)
PB5 (PCINT5)
PC7 (INT4 / ICP1 / CLKO)
PC6 (OC.1A / PCINT8)
Reset (PC1 / dW)
PC5 ( PCINT9/ OC.1B)
PC4 (PCINT10)
UCAP
(RXD1 / AIN1 / INT2) PD2
(RTS / AIN5 / INT6) PD6
(CTS / HWB / AIN6 / T0 / INT7) PD7
(
SS / PCINT0) PB0
(SCLK / PCINT1) PB1
(PDI / MOSI / PCINT2) PB2
AVCC
UVCC
TQFP32
(PCINT11 /AIN2 ) PC2
(OC.0B / INT0) PD0
VCC
XTAL1
(INT5/ AIN3) PD4
(TXD1 / INT3) PD3
(XCK AIN4 / PCINT12) PD5
PB3 (PDO / MISO / PCINT3)
GND
(PC0) XTAL2
UGND
PB4 (T1 / PCINT4)
28 27 26
1
2
3
4
5
6
7
24
23
22
21
20
19
18
1211109131415
(AIN0 / INT1) PD1
8
16
17
PB6 (PCINT6)
D- D+
2529303132
PB7 (PCINT7 / OC.0A / OC.1C)
PB5 (PCINT5)
PC7 (INT4 / ICP1 / CLKO)
PC6 (OC.1A / PCINT8)
Reset (PC1 / dW)
PC5 ( PCINT9/ OC.1B)
PC4 (PCINT10)
UCAP
(RXD1 / AIN1 / INT2) PD2
(RTS / AIN5 / INT6) PD6
/ HWB / AIN6 / T0 / INT7) PD7
(SS / PCINT0) PB0
(SCLK / PCINT1) PB1
(PDI / MOSI / PCINT2) PB2
AVCC