Datasheet

95
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
17.6.7 Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT1 when using any of the output compare units, independent of whether the
Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be
missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with vari-
able TOP values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is down counting.
The setup of the OC1x should be performed before setting the Data Direction Register for the port pin to output.
The easiest way of setting the OC1x value is to use the force output compare (FOC1x) strobe bits in Normal mode.
The OC1x Register keeps its value even when changing between waveform generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the
COM1x1:0 bits will take effect immediately.
17.7 Compare Match Output Unit
The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0
bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control
the OC1x pin output source. Figure 16-5 shows a simplified schematic of the logic affected by the COM1x1:0 bit
setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O
Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the
OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a System Reset occur, the OC1x
Register is reset to “0”.
Figure 17-5. Compare Match Output Unit, Schematic
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform Generator if either
of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direc-
tion Register (DDR) for the port pin. The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set as
output before the OC1x value is visible on the pin. The port override function is generally independent of the Wave-
form Generation mode, but there are some exceptions. Refer to Table 16-2, Table 16-3 and Table 16-4 for details.
PORT
DDR
DQ
DQ
OCnx
Pin
OCnx
DQ
Waveform
Generator
COMnx1
COMnx0
0
1
DATA BU S
FOCnx
clk
I/O