Datasheet

71
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the nor-
mal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering
synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The
synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR0 Register access may seem complex, but this is not case. When the double buffering is enabled, the
CPU has access to the OCR0 Buffer Register, and if double buffering is disabled the CPU will access the OCR0
directly.
15.5.1 Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to
the Force Output Compare (FOC0) bit. Forcing compare match will not set the OCF0 Flag or reload/clear the timer,
but the OC0 pin will be updated as if a real compare match had occurred (the COM0[1:0] bits settings define
whether the OC0 pin is set, cleared or toggled).
15.5.2 Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any compare match that occur in the next timer clock
cycle, even when the timer is stopped. This feature allows OCR0 to be initialized to the same value as TCNT0 with-
out triggering an interrupt when the Timer/Counter clock is enabled.
15.5.3 Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are
risks involved when changing TCNT0 when using the output compare unit, independently of whether the
Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0 value, the compare match will be
missed, resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM
when the counter is downcounting.
The setup of the OC0 should be performed before setting the Data Direction Register for the port pin to output. The
easiest way of setting the OC0 value is to use the Force Output Compare (FOC0) strobe bits in Normal mode. The
OC0 Register keeps its value even when changing between waveform generation modes.
Be aware that the COM0[1:0] bits are not double buffered together with the compare value. Changing the
COM0[1:0] bits will take effect immediately.
15.6 Compare Match Output Unit
The Compare Output mode (COM0[1:0]) bits have two functions. The Waveform Generator uses the COM0[1:0]
bits for defining the Output Compare (OC0) state at the next compare match. Also, the COM0[1:0] bits control the
OC0 pin output source. Figure 14-4 shows a simplified schematic of the logic affected by the COM0[1:0] bit setting.
The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port Con-
trol Registers (DDR and PORT) that are affected by the COM0[1:0] bits are shown. When referring to the OC0
state, the reference is for the internal OC0 Register, not the OC0 pin. If a System Reset occur, the OC0 Register is
reset to “0”.