Datasheet

67
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU General Control Register (MCUCR)
define whether the External Interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activ-
ity on the pin will cause an interrupt request even if INT0 is configured as an output. The corresponding interrupt of
External Interrupt Request 0 is executed from the INT0 interrupt vector.
• Bit 5 – INT2: External Interrupt Request 2 Enable
When the INT2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control2 bit (ISC2) in the MCU Control and Status Register (MCUCSR) defines
whether the External Interrupt is activated on rising or falling edge of the INT2 pin. Activity on the pin will cause an
interrupt request even if INT2 is configured as an output. The corresponding interrupt of External Interrupt Request
2 is executed from the INT2 Interrupt Vector.
14.1.4 GIFR – General Interrupt Flag Register
• Bit 7 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the I-bit in
SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
This flag is always cleared when INT1 is configured as a level interrupt.
• Bit 6 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding interrupt vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
This flag is always cleared when INT0 is configured as a level interrupt.
• Bit 5 – INTF2: External Interrupt Flag 2
When an event on the INT2 pin triggers an interrupt request, INTF2 becomes set (one). If the I-bit in SREG and the
INT2 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when
the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. Note that when
entering some sleep modes with the INT2 interrupt disabled, the input buffer on this pin will be disabled. This may
cause a logic change in internal signals which will set the INTF2 Flag. See “Digital Input Enable and Sleep Modes”
on page 54 for more information.
Bit 76543210
INTF1 INTF0 INTF2
– – – – –GIFR
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0