Datasheet

66
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt
mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 13-2.
The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last
longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction
to generate an interrupt.
14.1.2 MCUCSR – MCU Control and Status Register
• Bit 6 – ISC2: Interrupt Sense Control 2
The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and the correspond-
ing interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on INT2 activates the interrupt. If ISC2
is written to one, a rising edge on INT2 activates the interrupt. Edges on INT2 are registered asynchronously.
Pulses on INT2 wider than the minimum pulse width given in Table 13-3 will generate an interrupt. Shorter pulses
are not guaranteed to generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it is
recommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then, the ISC2 bit can
be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit
(INTF2) in the GIFR Register before the interrupt is re-enabled.
14.1.3 GICR – General Interrupt Control Register
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is
enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU General Control Register (MCUCR)
define whether the External Interrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activ-
ity on the pin will cause an interrupt request even if INT1 is configured as an output. The corresponding interrupt of
External Interrupt Request 1 is executed from the INT1 interrupt Vector.
Table 14-2. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 generates an interrupt request.
0 1 Any logical change on INT0 generates an interrupt request.
1 0 The falling edge of INT0 generates an interrupt request.
1 1 The rising edge of INT0 generates an interrupt request.
Bit 76543210
JTD ISC2 – JTRF WDRF BORF EXTRF PORF MCUCSR
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value 0 0 0 See Bit Description
Table 14-3. Asynchronous External Interrupt Characteristics
Symbol Parameter Condition Min Typ Max Units
t
INT
Minimum pulse width for asynchronous
external interrupt
50 ns
Bit 76543210
INT1 INT0 INT2
– – – IVSEL IVCE GICR
Read/Write R/W R/W R/W R R R R/W R/W
Initial Value 0 0 0 0 0 0 0 0