Datasheet

243
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When
BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read
the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and SPMEN bits in SPMCR. When an LPM
instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of
the Fuse Low bits (FLB) will be loaded in the destination register as shown below. Refer to Table 26-4 on page 268
for a detailed description and mapping of the Fuse Low bits.
Similarly, when reading the Fuse High bits, load $0003 in the Z-pointer. When an LPM instruction is executed
within three cycles after the BLBSET and SPMEN bits are set in the SPMCR, the value of the Fuse High bits (FHB)
will be loaded in the destination register as shown below. Refer to Table 26-3 on page 267 for detailed description
and mapping of the Fuse High bits.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unprogrammed, will be
read as one.
26.8.10 Preventing Flash Corruption
During periods of low V
CC,
the Flash program can be corrupted because the supply voltage is too low for the CPU
and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the
same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a regular write
sequence to the Flash requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute
instructions incorrectly, if the supply voltage for executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is sufficient):
1. If there is no need for a Boot Loader update in the system, program the Boot Loader Lock bits to prevent
any Boot Loader software updates.
2. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done
by enabling the internal Brown-out Detector (BOD) if the operating voltage matches the detection level. If
not, an external low V
CC
Reset Protection circuit can be used. If a reset occurs while a write operation is in
progress, the write operation will be completed provided that the power supply voltage is sufficient.
3. Keep the AVR core in Power-down Sleep mode during periods of low V
CC
. This will prevent the CPU from
attempting to decode and execute instructions, effectively protecting the SPMCR Register and thus the
Flash from unintentional writes.
26.8.11 Programming Time for Flash when using SPM
The Calibrated RC Oscillator is used to time Flash accesses. Table 25-5 shows the typical programming time for
Flash accesses from the CPU.
Bit 76543210
Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1
Bit 76543210
Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0
Bit 76543210
Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0
Table 26-5. SPM Programming Time.
Symbol Min Programming Time Max Programming Time
Flash write (Page Erase, Page Write,
and write Lock bits by SPM)
3.7ms 4.5ms