Datasheet

155
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
20.11 Register Description
20.11.1 UDR – USART I/O Data Register
The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address
referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for
data written to the UDR Register location. Reading the UDR Register location will return the contents of the
Receive Data Buffer Register (RXB).
For 5-bit, 6-bit, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the
Receiver.
The transmit buffer can only be written when the UDRE Flag in the UCSRA Register is set. Data written to UDR
when the UDRE Flag is not set, will be ignored by the USART Transmitter. When data is written to the transmit buf-
fer, and the Transmitter is enabled, the Transmitter will load the data into the transmit Shift Register when the Shift
Register is empty. Then the data will be serially transmitted on the TxD pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the receive buffer is
accessed. Due to this behavior of the receive buffer, do not use read modify write instructions (SBI and CBI) on this
location. Be careful when using bit test instructions (SBIC and SBIS), since these also will change the state of the
FIFO.
20.11.2 UCSRA – USART Control and Status Register A
• Bit 7 – RXC: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty
(that is, does not contain any unread data). If the receiver is disabled, the receive buffer will be flushed and conse-
quently the RXC bit will become zero. The RXC Flag can be used to generate a Receive Complete interrupt (see
description of the RXCIE bit).
• Bit 6 – TXC: USART Transmit Complete
This flag bit is set when the entire frame in the transmit Shift Register has been shifted out and there are no new
data currently present in the transmit buffer (UDR). The TXC Flag bit is automatically cleared when a transmit com-
plete interrupt is executed, or it can be cleared by writing a one to its bit location. The TXC Flag can generate a
Transmit Complete interrupt (see description of the TXCIE bit).
• Bit 5 – UDRE: USART Data Register Empty
The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is
empty, and therefore ready to be written. The UDRE Flag can generate a Data Register empty Interrupt (see
description of the UDRIE bit).
UDRE is set after a reset to indicate that the transmitter is ready.
• Bit 4 – FE: Frame Error
Bit 76543210
RXB[7:0] UDR (Read)
TXB[7:0] UDR (Write)
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Bit 76543210
RXC TXC UDRE FE DOR PE U2X MPCM UCSRA
Read/Write R R/W R R R R R/W R/W
Initial Value00100000