Datasheet

139
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
fosc XTAL pin frequency (System Clock).
20.3.1 Internal Clock Generation – The Baud Rate Generator
Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The
description in this section refers to Figure 19-2.
The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable pres-
caler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value
each time the counter has counted down to zero or when the UBRRL Register is written. A clock is generated each
time the counter reaches zero. This clock is the baud rate generator clock output (= fosc/(UBRR+1)). The Trans-
mitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator
output is used directly by the receiver’s clock and data recovery units. However, the recovery units use a state
machine that uses 2, 8 or 16 states depending on mode set by the state of the UMSEL, U2X and DDR_XCK bits.
Table 19-1 contains equations for calculating the baud rate (in bits per second) and for calculating the UBRR value
for each mode of operation using an internally generated clock source.
Note: 1. The baud rate is defined to be the transfer rate in bit per second (bps).
BAUD Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)
Some examples of UBRR values for some system clock frequencies are found in Table 19-9 (see page 172).
20.3.2 Double Speed Operation (U2X)
The transfer rate can be doubled by setting the U2X bit in UCSRA. Setting this bit only has effect for the asynchro-
nous operation. Set this bit to zero when using synchronous operation.
Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for
asynchronous communication. Note however that the receiver will in this case only use half the number of samples
(reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and
system clock are required when this mode is used. For the Transmitter, there are no downsides.
20.3.3 External Clock
External clocking is used by the synchronous slave modes of operation. The description in this section refers to
Figure 19-2 for details.
External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-sta-
bility. The output from the synchronization register must then pass through an edge detector before it can be used
Table 20-1. Equations for Calculating Baud Rate Register Setting
Operating Mode
Equation for Calculating
Baud Rate
(1)
Equation for Calculating
UBRR Value
Asynchronous Normal Mode
(U2X = 0)
Asynchronous Double Speed Mode (U2X
= 1)
Synchronous Master Mode
BAUD
f
OSC
16 UBRR 1+
---------------------------------------=
UBRR
f
OSC
16BAUD
------------------------ 1–=
BAUD
f
OSC
8 UBRR 1+
-----------------------------------=
UBRR
f
OSC
8BAUD
-------------------- 1–=
BAUD
f
OSC
2 UBRR 1+
-----------------------------------=
UBRR
f
OSC
2BAUD
-------------------- 1–=