Datasheet

107
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
Note: 1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
17.10.2 TCCR1B – Timer/Counter1 Control Register B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is activated, the
input from the Input Capture Pin (ICP1) is filtered. The filter function requires four successive equal valued samples
of the ICP1 pin for changing its output. The Input Capture is therefore delayed by four Oscillator cycles when the
Noise Canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture event. When the
ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ICES1 bit is written to one, a
rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Reg-
ister (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture
Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the
TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be written to zero
when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
40 1 0 0
CTC OCR1A Immediate MAX
50 1 0 1
Fast PWM, 8-bit 0x00FF BOTTOM TOP
60 1 1 0
Fast PWM, 9-bit 0x01FF BOTTOM TOP
70 1 1 1
Fast PWM, 10-bit 0x03FF BOTTOM TOP
81 0 0 0
PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM
91 0 0 1
PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM
10 1 0 1 0
PWM, Phase Correct ICR1 TOP BOTTOM
11 1 0 1 1
PWM, Phase Correct OCR1A TOP BOTTOM
12 1 1 0 0
CTC ICR1 Immediate MAX
13 1 1 0 1
Reserved – – –
14 1 1 1 0
Fast PWM ICR1 BOTTOM TOP
15 1 1 1 1
Fast PWM OCR1A BOTTOM TOP
Table 17-5. Waveform Generation Mode Bit Description
(1)
Mode WGM13
WGM12
(CTC1)
WGM11
(PWM11)
WGM10
(PWM10)
Timer/Counter Mode of
Operation TOP
Update of
OCR1x
TOV1 Flag Set
on
Bit 765 4 3210
ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 TCCR1B
Read/Write R/W R/W R R/W R/W R/W R/W R/W
Initial Value000 0 0000