Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VQFN 44 (7x7) 8-Bit 16 MHz I/O number 32

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Table Of Contents

Features
1. Pin Configurations
2. Overview
- 2.1 Block Diagram
- 2.2 Pin Descriptions
3. Resources
4. Data Retention
5. About Code Examples
6. Capacitive touch sensing
7. AVR CPU Core
- 7.1 Overview
- 7.2 ALU – Arithmetic Logic Unit
- 7.3 Status Register
  - 7.3.1 SREG – AVR Status Register
- 7.4 General Purpose Register File
  - 7.4.1 The X-register, Y-register and Z-register
- 7.5 Stack Pointer
  - 7.5.1 SPH and SPL – Stack Pointer High and Low Register
- 7.6 Instruction Execution Timing
- 7.7 Reset and Interrupt Handling
  - 7.7.1 Interrupt Response Time
8. AVR Memories
- 8.1 Overview
- 8.2 In-System Reprogrammable Flash Program Memory
- 8.3 SRAM Data Memory
  - 8.3.1 Data Memory Access Times
- 8.4 EEPROM Data Memory
- 8.5 I/O Memory
- 8.6 Register Description
9. System Clock and Clock Options
- 9.1 Clock Systems and their Distribution
- 9.2 Clock Sources
- 9.3 Default Clock Source
- 9.4 Crystal Oscillator
- 9.5 Low-frequency Crystal Oscillator
- 9.6 External RC Oscillator
- 9.7 Calibrated Internal RC Oscillator
- 9.8 External Clock
- 9.9 Timer/Counter Oscillator
- 9.10 Register Description
  - 9.10.1 OSCCAL – Oscillator Calibration Register
10. Power Management and Sleep Modes
- 10.1 Sleep Modes
- 10.2 Idle Mode
- 10.3 ADC Noise Reduction Mode
- 10.4 Power-down Mode
- 10.5 Power-save Mode
- 10.6 Standby Mode
- 10.7 Extended Standby Mode
- 10.8 Minimizing Power Consumption
- 10.9 Register Description
  - 10.9.1 MCUCR – MCU Control Register
11. System Control and Reset
- 11.1 Resetting the AVR
- 11.2 Reset Sources
- 11.3 Internal Voltage Reference
  - 11.3.1 Voltage Reference Enable Signals and Start-up Time
- 11.4 Watchdog Timer
- 11.5 Register Description
  - 11.5.1 MCUCSR – MCU Control and Status Register
  - 11.5.2 WDTCR – Watchdog Timer Control Register
12. Interrupts
- 12.1 Interrupt Vectors in ATmega32A
  - 12.1.1 Moving Interrupts Between Application and Boot Space
- 12.2 Register Description
  - 12.2.1 GICR – General Interrupt Control Register
13. I/O Ports
- 13.1 Overview
- 13.2 Ports as General Digital I/O
- 13.3 Alternate Port Functions
- 13.4 Register Description
14. External Interrupts
- 14.1 Register Description
15. 8-bit Timer/Counter0 with PWM
- 15.1 Features
- 15.2 Overview
  - 15.2.1 Registers
  - 15.2.2 Definitions
- 15.3 Timer/Counter Clock Sources
- 15.4 Counter Unit
- 15.5 Output Compare Unit
- 15.6 Compare Match Output Unit
  - 15.6.1 Compare Output Mode and Waveform Generation
- 15.7 Modes of Operation
- 15.8 Timer/Counter Timing Diagrams
- 15.9 Register Description
16. Timer/Counter0 and Timer/Counter1 Prescalers
- 16.1 Overview
- 16.2 Internal Clock Source
- 16.3 Prescaler Reset
- 16.4 External Clock Source
- 16.5 Register Description
  - 16.5.1 SFIOR – Special Function IO Register
17. 16-bit Timer/Counter1
- 17.1 Features
- 17.2 Overview
- 17.3 Accessing 16-bit Registers
  - 17.3.1 Reusing the Temporary High Byte Register
- 17.4 Timer/Counter Clock Sources
- 17.5 Counter Unit
- 17.6 Input Capture Unit
- 17.7 Compare Match Output Unit
  - 17.7.1 Compare Output Mode and Waveform Generation
- 17.8 Modes of Operation
- 17.9 Timer/Counter Timing Diagrams
- 17.10 Register Description
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 18.1 Features
- 18.2 Overview
  - 18.2.1 Registers
  - 18.2.2 Definitions
- 18.3 Timer/Counter Clock Sources
- 18.4 Counter Unit
- 18.5 Output Compare Unit
- 18.6 Compare Match Output Unit
  - 18.6.1 Compare Output Mode and Waveform Generation
- 18.7 Modes of Operation
- 18.8 Timer/Counter Timing Diagrams
- 18.9 Asynchronous Operation of the Timer/Counter
- 18.10 Timer/Counter Prescaler
- 18.11 Register Description
19. SPI – Serial Peripheral Interface
- 19.1 Features
- 19.2 Overview
- 19.3 SS Pin Functionality
- 19.4 Data Modes
20. USART
- 20.1 Features
- 20.2 Overview
  - 20.2.1 AVR USART vs. AVR UART – Compatibility
- 20.3 Clock Generation
- 20.4 Frame Formats
  - 20.4.1 Parity Bit Calculation
- 20.5 USART Initialization
- 20.6 Data Transmission – The USART Transmitter
- 20.7 Data Reception – The USART Receiver
- 20.8 Asynchronous Data Reception
- 20.9 Multi-processor Communication Mode
  - 20.9.1 Using MPCM
- 20.10 Accessing UBRRH/ UCSRC Registers
  - 20.10.1 Write Access
  - 20.10.2 Read Access
- 20.11 Register Description
- 20.12 Examples of Baud Rate Setting
21. Two-wire Serial Interface
- 21.1 Features
- 21.2 Two-wire Serial Interface Bus Definition
  - 21.2.1 TWI Terminology
  - 21.2.2 Electrical Interconnection
- 21.3 Data Transfer and Frame Format
- 21.4 Multi-master Bus Systems, Arbitration and Synchronization
- 21.5 Overview of the TWI Module
- 21.6 Using the TWI
- 21.7 Transmission Modes
- 21.8 Multi-master Systems and Arbitration
- 21.9 Register Description
22. Analog Comparator
- 22.1 Overview
- 22.2 Analog Comparator Multiplexed Input
- 22.3 Register Description
  - 22.3.1 SFIOR – Special Function IO Register
  - 22.3.2 ACSR – Analog Comparator Control and Status Register
23. Analog to Digital Converter
- 23.1 Features
- 23.2 Overview
- 23.3 Operation
- 23.4 Starting a Conversion
- 23.5 Prescaling and Conversion Timing
  - 23.5.1 Differential Gain Channels
- 23.6 Changing Channel or Reference Selection
  - 23.6.1 ADC Input Channels
  - 23.6.2 ADC Voltage Reference
- 23.7 ADC Noise Canceler
- 23.8 ADC Conversion Result
- 23.9 Register Description
24. JTAG Interface and On-chip Debug System
- 24.1 Features
- 24.2 Overview
- 24.3 TAP – Test Access Port
- 24.4 TAP Controller
- 24.5 Using the Boundary-scan Chain
- 24.6 Using the On-chip Debug System
- 24.7 On-chip Debug Specific JTAG Instructions
- 24.8 Using the JTAG Programming Capabilities
- 24.9 Register Description
  - 24.9.1 OCDR – On-chip Debug Register
- 24.10 Bibliography
25. IEEE 1149.1 (JTAG) Boundary-scan
- 25.1 Features
- 25.2 Overview
- 25.3 Data Registers
- 25.4 Boundary-scan Specific JTAG Instructions
- 25.5 Boundary-scan Chain
- 25.6 ATmega32A Boundary-scan Order
- 25.7 Boundary-scan Description Language Files
- 25.8 Register Description
  - 25.8.1 MCU Control and Status Register – MCUCSR
26. Boot Loader Support – Read-While-Write Self-Programming
- 26.1 Features
- 26.2 Overview
- 26.3 Application and Boot Loader Flash Sections
  - 26.3.1 Application Section
  - 26.3.2 BLS – Boot Loader Section
- 26.4 Read-While-Write and no Read-While-Write Flash Sections
  - 26.4.1 RWW – Read-While-Write Section
  - 26.4.2 NRWW – No Read-While-Write Section
- 26.5 Boot Loader Lock Bits
- 26.6 Entering the Boot Loader Program
- 26.7 Addressing the Flash during Self-Programming
- 26.8 Self-Programming the Flash
- 26.9 Register Description
  - 26.9.1 SPMCR – Store Program Memory Control Register
27. Memory Programming
- 27.1 Program And Data Memory Lock Bits
- 27.2 Fuse Bits
  - 27.2.1 Latching of Fuses
- 27.3 Signature Bytes
- 27.4 Calibration Byte
- 27.5 Page Size
- 27.6 Parallel Programming Parameters, Pin Mapping, and Commands
  - 27.6.1 Signal Names
- 27.7 Parallel Programming
- 27.8 SPI Serial Downloading
- 27.9 SPI Serial Programming Pin Mapping
- 27.10 Programming via the JTAG Interface
28. Electrical Characteristics
- 28.1 Absolute Maximum Ratings*
- 28.2 DC Characteristics
- 28.3 Speed Grades
- 28.4 Clock Characteristics
  - 28.4.1 External Clock Drive Waveforms
  - 28.4.2 External Clock Drive
- 28.5 System and Reset Characteristics
- 28.6 Two-wire Serial Interface Characteristics
- 28.7 SPI Timing Characteristics
- 28.8 ADC Characteristics
29. Typical Characteristics
- 29.1 Active Supply Current
- 29.2 Idle Supply Current
- 29.3 Power-down Supply Current
- 29.4 Power-save Supply Current
- 29.5 Standby Supply Current
- 29.6 Pin Pull-up
- 29.7 Pin Driver Strength
- 29.8 Pin Thresholds and Hysteresis
- 29.9 BOD Thresholds and Analog Comparator Offset
- 29.10 Internal Oscillator Speed
- 29.11 Current Consumption of Peripheral Units
- 29.12 Current Consumption in Reset and Reset Pulsewidth
30. Register Summary
31. Instruction Set Summary
32. Ordering Information
33. Packaging Information
- 33.1 44A
- 33.2 40P6
- 33.3 44M1
34. Errata
- 34.1 ATmega32A, rev. J to rev. K
- 34.2 ATmega32A, rev. G to rev. I
35. Datasheet Revision History
- 35.1 Rev. 8155E – 02/2014
- 35.2 Rev. 8155D – 10/2013
- 35.3 Rev. 8155C – 02/2011
- 35.4 Rev. 8155B – 07/2009
- 35.5 Rev. 8155A – 06/2008
Table of Contents

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ATmega32A [DATASHEET]

Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014

Figure 25-4. General Port Pin Schematic Diagram

(1)

Note: 1. See Boundary-scan description for details.

25.5.2 Boundary-scan and the Two-wire Interface

The 2 Two-wire Interface pins SCL and SDA have one additional control signal in the scan-chain; Two-wire Inter-

face Enable – TWIEN. As shown in Figure 24-5, the TWIEN signal enables a tri-state buffer with slew-rate control

in parallel with the ordinary digital port pins. A general scan cell as shown in Figure 24-9 is attached to the TWIEN

signal.

Notes: 1. A separate scan chain for the 50 ns spike filter on the input is not provided. The ordinary scan support for digital

port pins suffice for connectivity tests. The only reason for having TWIEN in the scan path, is to be able to discon-

nect the slew-rate control buffer when doing boundary-scan.

2. Make sure the OC and TWIEN signals are not asserted simultaneously, as this will lead to drive contention.

CLK

RPx

RRx

WPx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WPx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

CLK : I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BU S

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

PUExn

OCxn

ODxn

IDxn

PUExn: PULLUP ENABLE for pin Pxn

OCxn: OUTPUT CONTROL for pin Pxn

ODxn: OUTPUT DATA to pin Pxn

IDxn: INPUT DATA from pin Pxn