Datasheet

17
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
Figure 8-3. On-chip Data SRAM Access Cycles
8.4 EEPROM Data Memory
The Atmel
®
AVR
®
ATmega32A contains 1024bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000
write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.
“Memory Programming” on page 248 contains a detailed description on EEPROM Programming in SPI, JTAG, or
Parallell Programming mode.
8.4.1 EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 8-1 on page 20. A self-timing function, however, lets the
user software detect when the next byte can be written. If the user code contains instructions that write the
EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on
Power-up/down. This causes the device for some period of time to run at a voltage lower than specified as mini-
mum for the clock frequency used. See “Preventing EEPROM Corruption” on page 18 for details on how to avoid
problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the
description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When
the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
8.4.2 EEPROM Write During Power-down Sleep Mode
When entering Power-down Sleep mode while an EEPROM write operation is active, the EEPROM write operation
will continue, and will complete before the Write Access time has passed. However, when the write operation is
completed, the Oscillator continues running, and as a consequence, the device does not enter Power-down
entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering
Power-down.
clk
WR
RD
Data
Data
Address
Address Valid
T1 T2 T3
Compute Address
Read
Write
CPU
Memory Access Instruction
Next Instruction