Datasheet

125
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
.
Note: 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored, but
the set or clear is done at TOP. See “Phase Correct PWM Mode” on page 127 for more details.
• Bit 2:0 – CS2[2:0]: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 17-6.
18.11.2 TCNT2 – Timer/Counter Register
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit
counter. Writing to the TCNT2 Register blocks (removes) the compare match on the following timer clock. Modify-
ing the counter (TCNT2) while the counter is running, introduces a risk of missing a compare match between
TCNT2 and the OCR2 Register.
18.11.3 OCR2 – Output Compare Register
The Output Compare Register contains an 8-bit value that is continuously compared with the counter value
(TCNT2). A match can be used to generate an output compare interrupt, or to generate a waveform output on the
OC2 pin.
Table 18-5. Compare Output Mode, Phase Correct PWM Mode
(1)
COM21 COM20 Description
0 0 Normal port operation, OC2 disconnected.
01Reserved
1 0 Clear OC2 on compare match when up-counting. Set OC2 on compare match
when downcounting.
1 1 Set OC2 on compare match when up-counting. Clear OC2 on compare match
when downcounting.
Table 18-6. Clock Select Bit Description
CS22 CS21 CS20 Description
0 0 0 No clock source (Timer/Counter stopped).
001
clk
T2S
/(No prescaling)
010
clk
T2S
/8 (From prescaler)
011
clk
T2S
/32 (From prescaler)
100
clk
T2S
/64 (From prescaler)
101
clk
T2S
/128 (From prescaler)
110clk
T
2
S
/256 (From prescaler)
111clk
T
2
S
/1024 (From prescaler)
Bit 76543210
TCNT2[7:0] TCNT2
Read/Write R/WR/WR/WR/WR/WR/WR/WR/W
Initial Value00000000
Bit 76543210
OCR2[7:0] OCR2
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value00000000