8-bit Microcontroller with 32KBytes In-System Programmable Flash ATmega32A Features • High-performance, Low-power Atmel®AVR® 8-bit Microcontroller • Advanced RISC Architecture • • • • • • • • • – 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 × 8 General Purpose Working Registers – Fully Static Operation – Up to 16MIPS Throughput at 16MHz – On-chip 2-cycle Multiplier High Endurance Non-volatile Memory segments – 32Kbytes of In-System Self-programmable Flash program memory – 1024B
1.
2. Overview The Atmel®AVR® ATmega32A is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega32A achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1.
one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
Port B also serves the functions of various special features of the ATmega32A as listed on page 56. 2.2.5 Port C (PC7:PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated.
5. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more details. 6.
. AVR CPU Core Overview This section discusses the Atmel®AVR® core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. Figure 7-1.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format.
• Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.
Figure 7-2. AVR CPU General Purpose Working Registers 7 0 Addr.
7.4.1 The X-register, Y-register and Z-register The registers R26:R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the Data Space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-3. Figure 7-3.
7.5.1 SPH and SPL – Stack Pointer High and Low Register Bit Read/Write Initial Value 7.6 15 14 13 12 11 10 9 8 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Instruction Execution Timing This section describes the general access timing concepts for instruction execution.
7.7 Reset and Interrupt Handling The Atmel®AVR® provides several different interrupt sources. These interrupts and the separate reset vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
Assembly Code Example in r16, SREG cli ; store SREG value ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit) C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<
8. AVR Memories 8.1 Overview This section describes the different memories in the ATmega32A. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega32A features an EEPROM Memory for data storage. All three memory spaces are linear and regular. 8.2 In-System Reprogrammable Flash Program Memory The ATmega32A contains 32Kbytes On-chip In-System Reprogrammable Flash memory for program storage.
8.3 SRAM Data Memory Figure 8-2 shows how the Atmel®AVR® ATmega32A SRAM Memory is organized. The lower 2144 Data Memory locations address the Register File, the I/O Memory, and the internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 2048 locations address the internal data SRAM. The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment.
Figure 8-3. On-chip Data SRAM Access Cycles T1 T2 T3 clkCPU Address Compute Address Address Valid Write Data WR Read Data RD Memory Access Instruction 8.4 Next Instruction EEPROM Data Memory The Atmel®AVR® ATmega32A contains 1024bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles.
8.4.3 Preventing EEPROM Corruption During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied. An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly.
8.6 8.6.1 Register Description EEARH and EEARL – EEPROM Address Register Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 – – – – – – EEAR9 EEAR8 EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL 7 6 5 4 3 2 1 0 R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 X X X X X X X X X • Bits [15:10] – Reserved Bits These bits are reserved bits in the ATmega32A and will always read as zero.
• Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential): 1. Wait until EEWE becomes zero. 2.
Assembly Code Example EEPROM_write: ; Wait for completion of previous write sbic EECR,EEWE rjmp EEPROM_write ; Set up address (r18:r17) in address register out EEARH, r18 out EEARL, r17 ; Write data (r16) to data register out EEDR,r16 ; Write logical one to EEMWE sbi EECR,EEMWE ; Start eeprom write by setting EEWE sbi EECR,EEWE ret C Code Example void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* Wait for completion of previous write */ while(EECR & (1<
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.
9. System Clock and Clock Options 9.1 Clock Systems and their Distribution Figure 9-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ““Power Management and Sleep Modes” on page 31. The clock systems are detailed Figure 9-1. Figure 9-1.
9.1.4 Asynchronous Timer Clock – clkASY The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external 32kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode. 9.1.5 ADC Clock – clkADC The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry.
For resonators, the maximum frequency is 8MHz with CKOPT unprogrammed and 16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 9-3.
Table 9-4. Start-up Times for the Crystal Oscillator Clock Selection (Continued) CKSEL0 SUT1:0 Start-up Time from Power-down and Power-save 1 01 16K CK – 1 10 16K CK 4.1ms Crystal Oscillator, fast rising power 1 11 16K CK 65ms Crystal Oscillator, slowly rising power Notes: Additional Delay from Reset (VCC = 5.0V) Recommended Usage Crystal Oscillator, BOD enabled 1.
Figure 9-3. External RC Configuration VCC NC R XTAL2 XTAL1 C GND The Oscillator can operate in four different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3:0 as shown in Table 9-6. Table 9-6. External RC Oscillator Operating Modes CKSEL3:0 Frequency Range (MHz) 0101 0.1 - 0.9 0110 0.9 - 3.0 0111 3.0 - 8.0 1000 8.0 - 12.0 When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 9-7. Table 9-7.
Table 9-8. Internal Calibrated RC Oscillator Operating Modes CKSEL3:0 0001 Note: Nominal Frequency (MHz) (1) 1.0 0010 2.0 0011 4.0 0100 8.0 1. The device is shipped with this option selected. When this Oscillator is selected, start-up times are determined by the SUT fuses as shown in Table 9-9. XTAL1 and XTAL2 should be left unconnected (NC). Table 9-9.
When this clock source is selected, start-up times are determined by the SUT fuses as shown in Table 9-10. Table 9-10. Start-up Times for the External Clock Selection SUT1:0 Start-up Time from Power-down and Power-save Additional Delay from Reset (VCC = 5.0V) 00 6 CK – 01 6 CK 4.
9.10 9.10.1 Register Description OSCCAL – Oscillator Calibration Register Bit Read/Write 7 6 5 4 3 2 1 0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value OSCCAL Device Specific Calibration Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value Writing the calibration byte to this address will trim the Internal Oscillator to remove process variations from the Oscillator frequency.
10. Power Management and Sleep Modes 10.1 Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. Figure 8-1 on page 25 presents the different clock systems in the ATmega32A, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 10-1 shows the different clock options and their wake-up sources.
required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 10.
10.7 Extended Standby Mode When the SM2:0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 10.8 Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system.
details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to VCC/2, the input buffer will use excessive power. 10.8.7 JTAG Interface and On-chip Debug System • If the On-chip debug system is enabled by the OCDEN Fuse and the chip enter Power down or Power save sleep mode, the main clock source remains enabled. In these sleep modes, this will contribute significantly to the total current consumption.
10.9 Register Description 10.9.1 MCUCR – MCU Control Register The MCU Control Register contains control bits for power management. Bit 7 6 5 4 3 2 1 0 SE SM2 SM1 SM0 ISC11 ISC10 ISC01 ISC00 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 MCUCR • Bit 7 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed.
11. System Control and Reset 11.1 Resetting the AVR During Reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – absolute jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations.
Figure 11-1. Reset Logic DATA BUS PORF BORF EXTRF WDRF JTRF MCU Control and Status Register (MCUCSR) Power-on Reset Circuit INTERNAL RESET Brown-out Reset Circuit BODEN BODLEVEL SPIKE FILTER Reset Circuit JTAG Reset Register Watchdog Timer COUNTER RESET Pull-up Resistor Watchdog Oscillator Clock Generator CK Delay Counters TIMEOUT CKSEL[3:0] SUT[1:0] 11.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit.
Figure 11-3. MCU Start-up, RESET Extended Externally VCC VPOT RESET TIME-OUT VRST tTOUT INTERNAL RESET 11.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see “System and Reset Characteristics” on page 299) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.
Figure 11-5. Brown-out Reset During Operation VCC VBOT- VBOT+ RESET tTOUT TIME-OUT INTERNAL RESET 11.2.4 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to “Watchdog Timer” on page 42 for details. Figure 11-6. Watchdog Reset During Operation CC CK 11.3 Internal Voltage Reference ATmega32A features an internal bandgap reference.
11.4 Watchdog Timer The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1MHz. This is the typical value at VCC = 5V. See characterization data for typical values at other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table 10-1 on page 44. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
11.5 Register Description 11.5.1 MCUCSR – MCU Control and Status Register The MCU Control and Status Register provides information on which reset source caused an MCU Reset.
1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog. • Bits 2:0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0 The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled.
12. Interrupts This section describes the specifics of the interrupt handling as performed in ATmega32A. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13. 12.1 Interrupt Vectors in ATmega32A Table 12-1. Vector No.
Table 12-2. Reset and Interrupt Vectors Placement(1) BOOTRST IVSEL 1 Note: Reset address Interrupt Vectors Start Address 0 $0000 $0002 1 1 $0000 Boot Reset Address + $0002 0 0 Boot Reset Address $0002 0 1 Boot Reset Address Boot Reset Address + $0002 1. The Boot Reset Address is shown in Table 25-6 on page 263. For the BOOTRST Fuse “1” means unprogrammed while “0” means programmed.
When the BOOTRST Fuse is unprogrammed, the Boot section size set to 4Kbytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels $000 RESET: $001 $002 Code Comments ldi r16,high(RAMEND); Main program start out SPH,r16 ldi ; Set Stack Pointer to top of RAM r16,low(RAMEND) $003 out SPL,r16 $004 sei $005 ; Enable interrupts xxx ; .
$382E sei $382F ; Enable interrupts xxx 12.1.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 12.2 Register Description 12.2.
Assembly Code Example Move_interrupts: ; Enable change of interrupt vectors ldi r16, (1<
13. I/O Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input).
13.2 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 12-2 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 13-2. General Digital I/O(1) PUD Q D DDxn Q CLR RESET WDx Q Pxn D PORTxn Q CLR WPx DATA BUS RDx RESET RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q clk I/O PUD: SLEEP: clkI/O: Note: 13.2.
Switching between input with pull-up and output low generates the same problem. The user must use either the tristate ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step. Table 12-1 summarizes the control signals for the pin value. Table 13-1. 13.2.2 Port Pin Configurations DDxn PORTxn PUD (in SFIOR) I/O Pull-up 0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low.
Figure 13-4. Synchronization when Reading a Software Assigned Pin Value SYSTEM CLK r16 INSTRUCTIONS 0xFF out PORTx, r16 nop in r17, PINx SYNC LATCH PINxn r17 0x00 0xFF tpd The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7.
Assembly Code Example(1) :. ; Define pull-ups and set outputs high ; Define directions for port pins ldi r16,(1<
reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode). The simplest method to ensure a defined level of an unused pin, is to enable the internal pullup. In this case, the pullup will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pullup or pulldown.
Table 13-2. Generic Description of Overriding Signals for Alternate Functions Signal Name Full Name Description PUOE Pull-up Override Enable If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010. PUOV Pull-up Override Value If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.
Table 13-3. Port A Pins Alternate Functions Port Pin Alternate Function PA7 ADC7 (ADC input channel 7) PA6 ADC6 (ADC input channel 6) PA5 ADC5 (ADC input channel 5) PA4 ADC4 (ADC input channel 4) PA3 ADC3 (ADC input channel 3) PA2 ADC2 (ADC input channel 2) PA1 ADC1 (ADC input channel 1) PA0 ADC0 (ADC input channel 0) Table 12-4 and Table 12-5 relate the alternate functions of Port A to the overriding signals shown in Figure 12-5 on page 56. Table 13-4.
13.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 12-6. Table 13-6.
OC0, Output Compare Match output: The PB3 pin can serve as an external output for the Timer/Counter0 Compare Match. The PB3 pin has to be configured as an output (DDB3 set (one)) to serve this function. The OC0 pin is also the output pin for the PWM mode timer function. • AIN0/INT2 – Port B, Bit 2 AIN0, Analog Comparator Positive input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator.
Table 13-8. 13.3.3 Overriding Signals for Alternate Functions in PB3:PB0 Signal Name PB3/OC0/AIN1 PB2/INT2/AIN0 PB1/T1 PB0/T0/XCK PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE OC0 ENABLE 0 0 UMSEL PVOV OC0 0 0 XCK OUTPUT DIEOE 0 INT2 ENABLE 0 0 DIEOV 0 1 0 0 DI – INT2 INPUT T1 INPUT XCK INPUT/T0 INPUT AIO AIN1 INPUT AIN0 INPUT – – Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 12-9.
• TDO – Port C, Bit 4 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin. The TD0 pin is tri-stated unless TAP states that shifts out data are entered. • TMS – Port C, Bit 3 TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0(1) Signal Name PC3/TMS PC2/TCK PC1/SDA PC0/SCL PUOE JTAGEN JTAGEN TWEN TWEN PUOV 1 1 PORTC1 • PUD PORTC0 • PUD DDOE JTAGEN JTAGEN TWEN TWEN DDOV 0 0 SDA_OUT SCL_OUT PVOE 0 0 TWEN TWEN PVOV 0 0 0 0 DIEOE JTAGEN JTAGEN 0 0 DIEOV 0 0 0 0 DI – – – – AIO TMS TCK SDA INPUT SCL INPUT Note: 13.3.4 1.
• OC1A – Port D, Bit 5 OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDD5 set (one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function. • OC1B – Port D, Bit 4 OC1B, Output Compare Match B output: The PD4 pin can serve as an external output for the Timer/Counter1 Output Compare B.
Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0 13.4 13.4.
13.4.5 PORTB – Port B Data Register Bit 13.4.6 7 6 5 4 3 2 1 0 PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 DDRB – Port B Data Direction Register Bit 13.4.
13.4.
14. External Interrupts The External Interrupts are triggered by the INT0, INT1, and INT2 pins. Observe that, if enabled, the interrupts will trigger even if the INT0:2 pins are configured as outputs. This feature provides a way of generating a software interrupt. The external interrupts can be triggered by a falling or rising edge or a low level (INT2 is only an edge triggered interrupt).
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 13-2. The value on the INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
• Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU General Control Register (MCUCR) define whether the External Interrupt is activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
15. 8-bit Timer/Counter0 with PWM 15.1 Features • • • • • • • 15.2 Single Compare Unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator External Event Counter 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV0 and OCF0) Overview Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1.
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). See “Output Compare Unit” on page 75. for details.
TOP Signalize that TCNT0 has reached maximum value. BOTTOM Signalize that TCNT0 has reached minimum value (zero). Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk T0 ). clk T0 can be generated from an external or internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped.
The OCR0 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR0 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free. The OCR0 Register access may seem complex, but this is not case.
Figure 15-4. Compare Match Output Unit, Schematic COMn1 COMn0 FOCn Waveform Generator D Q 1 OCn DATA BUS D 0 OCn Pin Q PORT D Q DDR clk I/O The general I/O port function is overridden by the Output Compare (OC0) from the Waveform Generator if either of the COM0[1:0] bits are set. However, the OC0 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin.
Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the normal mode, a new counter value can be written anytime. The output compare unit can be used to generate interrupts at some given time.
15.7.3 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOTTOM.
clock cycle. Setting the OCR0 equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.) 15.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM0[1:0] = 1) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.
OC0 Register at compare match between OCR0 and TCNT0 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnPCPWM = ----------------N 510 The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0 Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Figure 15-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 14-10 shows the setting of OCF0 in all modes except CTC mode. Figure 15-10. Timer/Counter Timing Diagram, Setting of OCF0, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 14-11 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.
Figure 15-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP BOTTOM OCRn BOTTOM + 1 TOP OCFn 15.9 15.9.
Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions. However, the functionality and location of these bits are compatible with previous versions of the timer. • Bit 5:4 – COM0[1:0]: Compare Match Output Mode These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 15-6. Clock Select Bit Description CS02 CS01 CS00 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/(No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T0 pin. Clock on falling edge. 1 1 1 External clock source on T0 pin.
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter0 occurs, that is, when the TOV0 bit is set in the Timer/Counter Interrupt Flag Register – TIFR. 15.9.
16. Timer/Counter0 and Timer/Counter1 Prescalers 16.1 Overview Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.2 Internal Clock Source The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
Each half period of the external clock applied must be longer than one system clock cycle to ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem).
16.5 16.5.1 Register Description SFIOR – Special Function IO Register Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 – ACME PUD PSR2 PSR10 Read/Write R/W R/W R/W R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 SFIOR • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is written to one, the Timer/Counter1 and Timer/Counter0 prescaler will be reset. The bit will be cleared by hardware after the operation is performed.
17. 16-bit Timer/Counter1 17.1 Features • • • • • • • • • • • 17.
Figure 17-1. 16-bit Timer/Counter Block Diagram(1) Count Clear Direction TOVn (Int.Req.) Control Logic clkTn Clock Select Edge Detector TOP Tn BOTTOM ( From Prescaler ) Timer/Counter TCNTn = =0 OCnA (Int.Req.) Waveform Generation = OCnA DATABUS OCRnA OCnB (Int.Req.) Fixed TOP Values Waveform Generation = OCRnB OCnB ( From Analog Comparator Ouput ) ICFn (Int.Req.) Edge Detector ICRn Noise Canceler ICPn TCCRnA Note: 17.2.1 TCCRnB 1.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture Pin (ICP1) or on the Analog Comparator pins (See “Analog Comparator” on page 205.) The Input Capture unit includes a digital filtering unit (Noise Canceler) for reducing the chance of capturing noise spikes. The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16-bit registers does not involve using the temporary register. To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit Timer Registers assuming that no interrupts updates the temporary register.
The following code examples show how to do an atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
The following code examples show how to do an atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Figure 17-2. Counter Unit Block Diagram DATA BUS (8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) Clear Direction Control Logic clkTn Edge Detector Tn ( From Prescaler ) TOP BOTTOM Signal description (internal signals): Count Increment or decrement TCNT1 by 1. Direction Select between increment and decrement. Clear Clear TCNT1 (set all bits to zero). clkT1 Timer/Counter clock. TOP Signalize that TCNT1 has reached maximum value.
The Input Capture unit is illustrated by the block diagram shown in Figure 16-3. The elements of the block diagram that are not directly a part of the Input Capture unit are gray shaded. The small “n” in register and bit names indicates the Timer/Counter number. Figure 17-3.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin (Figure 15-1 on page 89). The edge detector is also identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increases the delay by four system clock cycles.
Figure 17-4. Output Compare Unit, Block Diagram DATA BUS (8-bit) TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) TCNTnH (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) OCRnxL (8-bit) OCRnx (16-bit Register) = (16-bit Comparator ) OCFnx (Int.Req.) TOP BOTTOM Waveform Generator WGMn3:0 OCnx COMnx1:0 The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
17.6.7 Using the Output Compare Unit Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT1 when using any of the output compare units, independent of whether the Timer/Counter is running or not. If the value written to TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP values.
The design of the output compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation. See “Register Description” on page 112. The COM1x1:0 bits have no effect on the Input Capture unit. 17.7.1 Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.
Figure 17-6. CTC Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) TCNTn OCnA (Toggle) Period (COMnA1:0 = 1) 1 2 3 4 An interrupt can be generated at each time the counter value reaches the TOP value by either using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
The PWM resolution for fast PWM can be fixed to 8-bit, 9-bit, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX).
the TCNT1 matches TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set. Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However, if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A as TOP is clearly a better choice due to its double buffer feature.
TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. Figure 17-8.
ments. The PWM frequency for the output when using phase correct PWM can be calculated by the following equation: f clk_I/O f OCnxPCPWM = --------------------------2 N TOP The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). The extreme values for the OCR1x Register represent special cases when generating a PWM waveform output in the phase correct PWM mode.
Figure 17-9. Phase and Frequency Correct PWM Mode, Timing Diagram OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx / TOP Update and TOVn Interrupt Flag Set (Interrupt on Bottom) TCNTn OCnx (COMnx1:0 = 2) OCnx (COMnx1:0 = 3) Period 1 2 3 4 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM).
opposite logic values. If OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty cycle. 17.9 Timer/Counter Timing Diagrams The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering).
Figure 17-12. Timer/Counter Timing Diagram, no Prescaling clkI/O clkTn (clkI/O /1) TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOP - 1 TOP BOTTOM BOTTOM + 1 TOP - 1 TOP TOP - 1 TOP - 2 TOVn (FPWM) and ICFn (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) New OCRnx Value Figure 16-13 shows the same timing data, but with the prescaler enabled. Figure 17-13.
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to.
Table 16-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 17-4. Compare Output Mode, Phase Correct and Phase and Frequency Correct PWM (1) COM1A1/COM1B1 COM1A0/COM1B0 0 0 Normal port operation, OC1A/OC1B disconnected. 0 1 WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM13:0 settings, normal port operation, OC1A/OC1B disconnected.
Waveform Generation Mode Bit Description(1) Table 17-5.
• Bit 2:0 – CS12:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure 16-10 and Figure 16-11. Table 17-6. CS12 Clock Select Bit Description CS11 CS10 Description 0 0 0 No clock source (Timer/Counter stopped). 0 0 1 clkI/O/1 (No prescaling) 0 1 0 clkI/O/8 (From prescaler) 0 1 1 clkI/O/64 (From prescaler) 1 0 0 clkI/O/256 (From prescaler) 1 0 1 clkI/O/1024 (From prescaler) 1 1 0 External clock source on T1 pin.
OCR1B[7:0] OCR1BL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT1). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC1x pin. The Output Compare Registers are 16-bit in size.
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Overflow Interrupt is enabled. The corresponding Interrupt Vector (See “Interrupts” on page 45.) is executed when the TOV1 Flag, located in TIFR, is set. 17.10.
18. 8-bit Timer/Counter2 with PWM and Asynchronous Operation 18.1 Features • • • • • • • 18.2 Single Compare unit Counter Clear Timer on Compare Match (Auto Reload) Glitch-free, Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Sources (TOV2 and OCF2) Allows clocking from External 32kHz Watch Crystal Independent of the I/O Clock Overview Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module.
with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decrement) its value.
count Increment or decrement TCNT2 by 1. direction Selects between increment and decrement. clear Clear TCNT2 (set all bits to zero). clkT2 Timer/Counter clock. top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2).
Figure 18-3. Output Compare Unit, Block Diagram DATA BUS OCRn TCNTn = (8-bit Comparator ) OCFn (Int.Req.) top bottom Waveform Generator OCxy FOCn WGMn1:0 COMn1:0 The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence.
Be aware that the COM2[1:0] bits are not double buffered together with the compare value. Changing the COM2[1:0] bits will take effect immediately. 18.6 Compare Match Output Unit The Compare Output mode (COM21:0) bits have two functions. The Waveform Generator uses the COM2[1:0] bits for defining the Output Compare (OC2) state at the next compare match. Also, the COM2[1:0] bits control the OC2 pin output source. Figure 17-4 shows a simplified schematic of the logic affected by the COM2[1:0] bit setting.
PWM). For non-PWM modes the COM2[1:0] bits control whether the output should be set, cleared, or toggled at a compare match (See “Compare Match Output Unit” on page 123.). For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 128. 18.7.1 Normal Mode The simplest mode of operation is the Normal mode (WGM2[1:0] = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed.
maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency is defined by the following equation: f clk_I/O f OCn = ---------------------------------------------2 N 1 + OCRn The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 18.7.
The PWM frequency for the output can be calculated by the following equation: f clk_I/O f OCnPWM = ----------------N 256 The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM21:0 to 3 (see Table 17-5 on page 134). The actual OC2 value will only be visible on the port pin if the data direction for the port pin is set as output.
Figure 18-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 17-10 shows the setting of OCF2 in all modes except CTC mode. Figure 18-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn OCRn OCRn - 1 OCRn OCRn + 1 OCRn + 2 OCRn Value OCFn Figure 17-11 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.
Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Prescaler (fclk_I/O/8) clkI/O clkTn (clkI/O /8) TCNTn (CTC) TOP - 1 TOP OCRn BOTTOM BOTTOM + 1 TOP OCFn 18.9 Asynchronous Operation of the Timer/Counter When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted.
save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: 1. Write a value to TCCR2, TCNT2, or OCR2. 2. Wait until the corresponding Update Busy Flag in ASSR returns to zero. 3. Enter Power-save or Extended Standby mode. • When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes.
18.10 Timer/Counter Prescaler Figure 18-12. Prescaler for Timer/Counter2 clkT2S PSR2 clkT2S/1024 clkT2S/256 clkT2S/128 clkT2S/8 AS2 clkT2S/64 10-BIT T/C PRESCALER Clear TOSC1 clkT2S/32 clkI/O 0 CS20 CS21 CS22 TIMER/COUNTER2 CLOCK SOURCE clkT2 The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clk IO. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
• Bit 6, 3 – WGM2[1:0]: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 17-2 and “Modes of Operation” on page 124. Table 18-2.
. Table 18-5. Compare Output Mode, Phase Correct PWM Mode(1) COM21 COM20 0 0 Normal port operation, OC2 disconnected. 0 1 Reserved 1 0 Clear OC2 on compare match when up-counting. Set OC2 on compare match when downcounting. 1 1 Set OC2 on compare match when up-counting. Clear OC2 on compare match when downcounting. Note: Description 1. A special case occurs when OCR2 equals TOP and COM21 is set. In this case, the compare match is ignored, but the set or clear is done at TOP.
18.11.4 ‘ASSR – Asynchronous Status Register Bit 7 6 5 4 3 2 1 0 – – – – AS2 TCN2UB OCR2UB TCR2UB Read/Write R R R R R/W R R R Initial Value 0 0 0 0 0 0 0 0 ASSR • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter2 is clocked from a Crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin.
18.11.6 TIFR – Timer/Counter Interrupt Flag Register Bit 7 6 5 4 3 2 1 0 OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 TOV0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TIFR • Bit 7 – OCF2: Output Compare Flag 2 The OCF2 bit is set (one) when a compare match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt handling vector.
19. SPI – Serial Peripheral Interface 19.1 Features • • • • • • • • Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega32A and peripheral devices or between several AVR devices. Figure 19-1. SPI Block Diagram(1) DIVIDER /2/4/8/16/32/64/128 SPI2X SPI2X 19.
Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line.
Note: See “Alternate Functions of Port B” on page 59 for a detailed description of how to define the direction of the user defined SPI pins. The following code examples show how to initialize the SPI as a master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins.
The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.
19.3 SS Pin Functionality 19.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs except MISO which can be user configured as an output, and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is driven high.
• Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode. • Bit 3 – CPOL: Clock Polarity When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle.
Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR). • Bit 6 – WCOL: Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.
Figure 19-3. SPI Transfer Format with CPHA = 0 SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB Bit 6 Bit 1 Bit 5 Bit 2 Bit 4 Bit 3 Bit 3 Bit 4 Bit 2 Bit 5 Bit 1 Bit 6 LSB MSB Figure 19-4.
20. USART 20.1 Features • • • • • • • • • • • • 20.
Figure 20-1. USART Block Diagram(1) Clock Generator UBRR[H:L] OSC BAUD RATE GENERATOR SYNC LOGIC PIN CONTROL XCK Transmitter TX CONTROL UDR (Transmit) DATABUS PARITY GENERATOR TxD Receiver CLOCK RECOVERY RX CONTROL RECEIVE SHIFT REGISTER DATA RECOVERY PIN CONTROL UDR (Receive) PARITY CHECKER UCSRA Note: PIN CONTROL TRANSMIT SHIFT REGISTER UCSRB RxD UCSRC 1. Refer to Figure 1-1 on page 2, Table 12-14 on page 66, and Table 12-8 on page 61 for USART pin placement.
• Receiver Operation However, the receive buffering has two improvements that will affect the compatibility in some special cases: • A second Buffer Register has been added. The two Buffer Registers operate as a circular FIFO buffer. Therefore the UDR must only be read once for each incoming data! More important is the fact that the Error Flags (FE and DOR) and the 9th data bit (RXB8) are buffered with the data in the receive buffer.
fosc 20.3.1 XTAL pin frequency (System Clock). Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description in this section refers to Figure 19-2. The USART Baud Rate Register (UBRR) and the down-counter connected to it function as a programmable prescaler or baud rate generator.
by the Transmitter and receiver. This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: f OSC f XCK ----------4 Note that fosc depends on the stability of the system clock source. It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 20.3.
St Start bit, always low. (n) Data bits (0 to 8). P Parity bit. Can be odd or even. Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0, and USBS bits in UCSRB and UCSRC. The Receiver and Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Assembly Code Example(1) USART_Init: ; Set baud rate out UBRRH, r17 out UBRRL, r16 ; Enable receiver and transmitter ldi r16, (1<>8); UBRRL = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRB = (1<
The USART has to be initialized before the function can be used. For the assembly code, the data to be sent is assumed to be stored in Register R16.
Assembly Code Example(1) USART_Transmit: ; Wait for empty transmit buffer sbis UCSRA,UDRE rjmp USART_Transmit ; Copy 9th bit from r17 to TXB8 cbi UCSRB,TXB8 sbrc r17,0 sbi UCSRB,TXB8 ; Put LSB data (r16) into buffer, sends the data out UDR,r16 ret C Code Example(1) void USART_Transmit( unsigned int data ) { /* Wait for empty transmit buffer */ while ( !( UCSRA & (1<
TXC Flag is useful in half-duplex communication interfaces (like the RS485 standard), where a transmitting application must enter receive mode and free the communication bus immediately after completing the transmission. When the Transmit Compete Interrupt Enable (TXCIE) bit in UCSRB is set, the USART Transmit Complete Interrupt will be executed when the TXC Flag becomes set (provided that global interrupts are enabled).
Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get and return received data from buffer in r16, UDR ret C Code Example(1) unsigned char USART_Receive( void ) { /* Wait for data to be received */ while ( !(UCSRA & (1<
Assembly Code Example(1) USART_Receive: ; Wait for data to be received sbis UCSRA, RXC rjmp USART_Receive ; Get status and 9th bit, then data from buffer in r18, UCSRA in r17, UCSRB in r16, UDR ; If error, return -1 andi r18,(1<
20.7.3 Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the receiver state. The Receive Complete (RXC) Flag indicates if there are unread data present in the receive buffer. This flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (that is, does not contain any unread data). If the receiver is disabled (RXEN = 0), the receive buffer will be flushed and consequently the RXC bit will become zero.
function of the RxD port pin. The receiver buffer FIFO will be flushed when the receiver is disabled. Remaining data in the buffer will be lost. 20.7.7 Flushing the Receive Buffer The receiver buffer FIFO will be flushed when the Receiver is disabled, that is, the buffer will be emptied of its contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an error condition, read the UDR I/O location until the RXC Flag is cleared.
samples have logical high levels (the majority wins), the start bit is rejected as a noise spike and the receiver starts looking for the next high to low-transition. If however, a valid start bit is detected, the clock recovery logic is synchronized and the data recovery can begin. The synchronization process is repeated for each start bit. 20.8.2 Asynchronous Data Recovery When the receiver clock is synchronized to the start bit, the data recovery can begin.
generated baud rate of the receiver does not have a similar (see Table 19-2) base frequency, the receiver will not be able to synchronize the frames to the start bit. The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate.
The recommendations of the maximum receiver baud rate error was made under the assumption that the receiver and transmitter equally divides the maximum total error. There are two possible sources for the receivers baud rate error. The receiver’s system clock (XTAL) will always have some minor instability over the supply voltage range and the temperature range.
20.10 Accessing UBRRH/ UCSRC Registers The UBRRH Register shares the same I/O location as the UCSRC Register. Therefore some special consideration must be taken when accessing this I/O location. 20.10.1 Write Access When doing a write access of this I/O location, the high bit of the value written, the USART Register Select (URSEL) bit, controls which one of the two registers that will be written. If URSEL is zero during a write operation, the UBRRH value will be updated.
The following code example shows how to read the UCSRC Register contents. Assembly Code Example(1) USART_ReadUCSRC: ; Read UCSRC in r16,UBRRH in r16,UCSRC ret C Code Example(1) unsigned char USART_ReadUCSRC( void ) { unsigned char ucsrc; /* Read UCSRC */ ucsrc = UBRRH; ucsrc = UCSRC; return ucsrc; } Note: 1. See “About Code Examples” on page 6. The assembly code example returns the UCSRC value in r16.
20.11 Register Description 20.11.1 UDR – USART I/O Data Register Bit 7 6 5 4 3 2 1 0 RXB[7:0] UDR (Read) TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Register (TXB) will be the destination for data written to the UDR Register location.
This bit is set if the next character in the receive buffer had a Frame Error when received, that is, when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the receive buffer (UDR) is read. The FE bit is zero when the stop bit of received data is one. Always set this bit to zero when writing to UCSRA. • Bit 3 – DOR: Data OverRun This bit is set if a Data OverRun condition is detected.
• Bit 3 – TXEN: Transmitter Enable Writing this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled. The disabling of the Transmitter (writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed, that is, when the transmit Shift Register and transmit Buffer Register do not contain data to be transmitted. When disabled, the transmitter will no longer override the TxD port.
Table 20-5. UPM Bits Settings UPM1 UPM0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled, Even Parity 1 1 Enabled, Odd Parity • Bit 3 – USBS: Stop Bit Select This bit selects the number of Stop Bits to be inserted by the Transmitter. The Receiver ignores this setting. Table 20-6.
20.11.5 UBRRL and UBRRH – USART Baud Rate Registers Bit 15 14 13 12 URSEL – – – 11 10 9 8 UBRR[11:8] UBRRH UBRR[7:0] 7 Read/Write Initial Value 6 5 UBRRL 4 3 2 1 0 R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 The UBRRH Register shares the same I/O location as the UCSRC Register. See the “Accessing UBRRH/ UCSRC Registers” on page 165 section which describes how to access this register.
Table 20-9. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 1.0000MHz fosc = 1.8432MHz fosc = 2.0000MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.
Table 20-10. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 3.6864MHz fosc = 4.0000MHz fosc = 7.3728MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.
Table 20-11. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 11.0592MHz fosc = 8.0000MHz fosc = 14.7456MHz Baud Rate (bps) UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.
Table 20-12. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued) fosc = 16.0000MHz U2X = 0 Baud Rate (bps) U2X = 1 UBRR Error UBRR Error 2400 416 -0.1% 832 0.0% 4800 207 0.2% 416 -0.1% 9600 103 0.2% 207 0.2% 14.4k 68 0.6% 138 -0.1% 19.2k 51 0.2% 103 0.2% 28.8k 34 -0.8% 68 0.6% 38.4k 25 0.2% 51 0.2% 57.6k 16 2.1% 34 -0.8% 76.8k 12 0.2% 25 0.2% 115.2k 8 -3.5% 16 2.1% 230.4k 3 8.5% 8 -3.5% 250k 3 0.0% 7 0.0% 0.
21. Two-wire Serial Interface 21.1 Features • • • • • • • • • • 21.
21.2.1 TWI Terminology The following definitions are frequently encountered in this section. Table 21-1. 21.2.2 TWI Terminology Term Description Master The device that initiates and terminates a transmission. The master also generates the SCL clock. Slave The device addressed by a master. Transmitter The device placing data on the bus. Receiver The device reading data from the bus.
for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high. Figure 21-3. START, REPEATED START, and STOP Conditions SDA SCL STOP START START 21.3.3 REPEATED START STOP Address Packet Format All address packets transmitted on the TWI bus are nine bits long, consisting of seven address bits, one READ/WRITE control bit and an acknowledge bit.
Figure 21-5. Data Packet Format Data MSB Data LSB ACK 8 9 Aggregate SDA SDA from Transmitter SDA from receiverR SCL from Master 1 2 7 SLA+R/W 21.3.5 STOP, REPEATED START or Next Data Byte Data Byte Combining Address and Data Packets into a Transmission A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal.
Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively. Figure 21-7. SCL Synchronization between Multiple Masters TA low TA high SCL from Master A SCL from Master B SCL bus Line TBlow Masters Start Counting Low Period TBhigh Masters Start Counting High Period Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data.
• A REPEATED START and a STOP condition It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. 21.5 Overview of the TWI Module The TWI module is comprised of several submodules, as shown in Figure 20-9.
• TWBR = Value of the TWI Bit Rate Register • TWPS = Value of the prescaler bits in the TWI Status Register Note: 21.5.3 Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus line load. See Table 27-2 on page 300 for value of pull-up resistor. Bus Interface Unit This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware.
21.6 Using the TWI The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like reception of a byte or transmission of a START condition. Because the TWI is interrupt-based, the application software is free to carry on other operations during a TWI byte transfer.
4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a slave acknowledged the packet or not. 5. The application software should now examine the value of TWSR, to make sure that the address packet was successfully transmitted, and that the value of the ACK bit was as expected.
Assembly code example 3 in C example r16,TWSR andi r16, 0xF8 cpi Comments if ((TWSR & 0xF8) != START) ERROR(); r16, START Check value of TWI Status Register. Mask prescaler bits. If status different from START go to ERROR brne ERROR 4 ldi r16, SLA_W TWDR = SLA_W; out TWDR, r16 TWCR = (1<
Data: 8-bit data byte P: STOP condition SLA: Slave Address In Figure 20-12 to Figure 20-18, circles are used to indicate that the TWINT Flag is set. The numbers in the circles show the status code held in TWSR, with the prescaler bits masked to zero. At these points, actions must be taken by the application to continue or complete the TWI transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not, the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the transfer.
Figure 21-12.
Figure 21-13. Data Transfer in Master Receiver Mode VCC Device 1 Device 2 MASTER RECEIVER SLAVE TRANSMITTER ........ Device 3 R1 Device n R2 SDA SCL A START condition is sent by writing the following value to TWCR: TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 1 X 1 0 X 1 0 X TWEN must be written to one to enable the Two-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be set to clear the TWINT Flag.
Table 21-3.
Figure 21-15. Data Transfer in Slave Receiver Mode VCC Device 1 Device 2 SLAVE RECEIVER MASTER TRANSMITTER ........ Device 3 R1 Device n R2 SDA SCL To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR TWA6 TWA5 Value TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE Device’s Own Slave Address The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master.
Table 21-4.
Figure 21-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes.
The upper seven bits are the address to which the Two-wire Serial Interface will respond when addressed by a master. If the LSB is set, the TWI will respond to the general call address ($00), otherwise it will ignore the general call address. TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE Value 0 1 0 0 0 1 0 X TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable the acknowledgement of the device’s own slave address or the general call address.
Table 21-5.
21.7.5 Miscellaneous States There are two status codes that do not correspond to a defined TWI state, see Table 20-6. Status $F8 indicates that no relevant information is available because the TWINT Flag is not set. This occurs between other states, and when the TWI is not involved in a serial transfer. Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus error occurs when a START or STOP condition occurs at an illegal position in the format frame.
allowed to proceed with the transfer, and that no data will be lost in the process. An example of an arbitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. Figure 21-20. An Arbitration Example VCC Device 1 Device 2 Device 3 MASTER TRANSMITTER MASTER TRANSMITTER SLAVE RECEIVER ........
Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same slave. In this case, neither the slave nor any of the masters will know about the bus contention. • Two or more masters are accessing the same slave with different data or direction bit. In this case, arbitration will occur, either in the READ/WRITE bit or in the data bits.
21.9 21.9.1 Register Description TWBR – TWI Bit Rate Register Bit 7 6 5 4 3 2 1 0 TWBR7 TWBR6 TWBR5 TWBR4 TWBR3 TWBR2 TWBR1 TWBR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 TWBR • Bits 7:0 – TWI Bit Rate Register TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes.
• Bit 4 – TWSTO: TWI STOP Condition Bit Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed slave mode and releases the SCL and SDA lines to a high impedance state.
To calculate bit rates, see “Bit Rate Generator Unit” on page 182. The value of TWPS1:0 is used in the equation. 21.9.4 TWDR – TWI Data Register Bit 7 6 5 4 3 2 1 0 TWD7 TWD6 TWD5 TWD4 TWD3 TWD2 TWD1 TWD0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 1 1 1 1 1 1 1 1 TWDR In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received.
22. Analog Comparator 22.1 Overview The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’s output can be set to trigger the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate interrupt, exclusive to the Analog Comparator.
Table 22-1. 22.3 22.3.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator Interrupt is activated. When written logic zero, the interrupt is disabled. • Bit 2 – ACIC: Analog Comparator Input Capture Enable When written logic one, this bit enables the Input Capture function in Timer/Counter1 to be triggered by the Analog Comparator.
23. Analog to Digital Converter 23.1 Features • • • • • • • • • • • • • • • 23.2 10-bit Resolution 0.5 LSB Integral Non-linearity ±2 LSB Absolute Accuracy 13 - 260 µs Conversion Time Up to 15kSPS at Maximum Resolution 8 Multiplexed Single Ended Input Channels 7 Differential Input Channels 2 Differential Input Channels with Optional Gain of 10x and 200x Optional Left adjustment for ADC Result Readout 0 - VCC ADC Input Voltage Range Selectable 2.
Figure 23-1. Analog to Digital Converter Block Schematic ADC CONVERSION COMPLETE IRQ INTERRUPT FLAGS ADTS[2:0] TRIGGER SELECT ADC[9:0] ADPS1 0 ADC DATA REGISTER (ADCH/ADCL) ADPS0 ADPS2 ADIF ADATE ADEN ADSC MUX1 15 ADC CTRL. & STATUS REGISTER (ADCSRA) MUX0 MUX3 MUX2 MUX4 ADLAR REFS0 REFS1 ADC MULTIPLEXER SELECT (ADMUX) ADIE ADIF 8-BIT DATA BUS AVCC PRESCALER START GAIN SELECTION CHANNEL SELECTION MUX DECODER CONVERSION LOGIC INTERNAL 2.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power saving sleep modes. The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL.
this mode the ADC will perform successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not. If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be read as one during a conversion, independently of how the conversion was started. Prescaling and Conversion Timing Figure 23-3.
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, see Table 22-1. Figure 23-4.
Figure 23-7. ADC Timing Diagram, Free Running Conversion One Conversion Cycle Number 11 12 Next Conversion 13 1 2 3 4 ADC Clock ADSC ADIF ADCH MSB of Result ADCL LSB of Result Sample & Hold Conversion Complete Table 23-1. ADC Conversion Time Condition Sample & Hold (Cycles from Start of Conversion) Conversion Time (Cycles) First conversion 13.5 25 Normal conversions, single ended 1.5 13 2 13.5 1.5/2.5 13/14 Auto Triggered conversions Normal conversions, differential 23.5.
23.6 Changing Channel or Reference Selection The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channels and reference selection only takes place at a safe point during the conversion. The channel and reference selection is continuously updated until a conversion is started. Once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the ADC.
AVCC is connected to the ADC through a passive switch. The internal 2.56V reference is generated from the internal bandgap reference (VBG ) through an internal amplifier. In either case, the external AREF pin is directly connected to the ADC, and the reference voltage can be made more immune to noise by connecting a capacitor between the AREF pin and ground. VREF can also be measured at the AREF pin with a high impedant voltmeter.
Figure 23-8. Analog Input Circuitry IIH ADCn 1..100 kΩ CS/H= 14 pF IIL VCC/2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. Keep analog signal paths as short as possible. Make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digital tracks. 2.
23.7.3 Offset Compensation Schemes The gain stage has a built-in offset cancellation circuitry that nulls the offset of differential measurements as much as possible. The remaining offset in the analog path can be measured directly by selecting the same channel for both differential inputs. This offset residue can be then subtracted in software from the measurement results. Using this kind of software based offset correction, offset on any channel can be reduced below one LSB. 23.7.
Figure 23-12. Integral Non-linearity (INL) Output Code INL Ideal ADC Actual ADC VREF Input Voltage • Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 23-13.
For single ended conversion, the result is V IN 1024 ADC = -------------------------V REF where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 22-3 on page 222 and Table 22-4 on page 223). 0x000 represents analog ground, and 0x3FF represents the selected reference voltage minus one LSB.
Table 23-2. Correlation between Input Voltage and Output Codes VADCn Read code Corresponding Decimal Value VADCm + VREF/GAIN 0x1FF 511 VADCm + 511/512 VREF/GAIN 0x1FF 511 VADCm + 510/512 VREF/GAIN 0x1FE 510 :. :. :. VADCm + 1/512 VREF/GAIN 0x001 1 VADCm 0x000 0 VADCm - 1/512 VREF/GAIN 0x3FF -1 :. :. :. VADCm - 511/512 VREF/GAIN 0x201 -511 VADCm - VREF/GAIN 0x200 -512 Example: ADMUX = 0xED (ADC3 - ADC2, 10x gain, 2.
23.9 23.9.1 Register Description ADMUX – ADC Multiplexer Selection Register Bit 7 6 5 4 3 2 1 0 REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 ADMUX • Bit 7:6 – REFS1:0: Reference Selection Bits These bits select the voltage reference for the ADC, as shown in Table 22-3.
Table 23-4. Positive Differential Input Negative Differential Input Gain 01100 ADC2 ADC2 10x 01101 ADC3 ADC2 10x 01110 ADC2 ADC2 200x 01111 ADC3 ADC2 200x 10000 ADC0 ADC1 1x 10001 ADC1 ADC1 1x ADC2 ADC1 1x 10011 ADC3 ADC1 1x 10100 ADC4 ADC1 1x 10101 ADC5 ADC1 1x 10110 ADC6 ADC1 1x 10111 ADC7 ADC1 1x 11000 ADC0 ADC2 1x 11001 ADC1 ADC2 1x 11010 ADC2 ADC2 1x 11011 ADC3 ADC2 1x 11100 ADC4 ADC2 1x 11101 ADC5 ADC2 1x MUX4:0 10010 23.9.
• Bit 5 – ADATE: ADC Auto Trigger Enable When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting the ADC Trigger Select bits, ADTS in SFIOR. • Bit 4 – ADIF: ADC Interrupt Flag This bit is set when an ADC conversion completes and the Data Registers are updated. The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
23.9.3.2 ADLAR = 1 Bit Read/Write Initial Value 15 14 13 12 11 10 9 8 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 – – – – – – ADCL 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 When an ADC conversion is complete, the result is found in these two registers. If differential channels are used, the result is presented in two’s complement form.
24. JTAG Interface and On-chip Debug System 24.1 Features • JTAG (IEEE std. 1149.1 Compliant) Interface • Boundary-scan Capabilities According to the IEEE std. 1149.
• TDO: Test Data Out. Serial output data from Instruction Register or Data Register. The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT – which is not provided. When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is cleared, the TAP input signals are internally pulled high and the JTAG is enabled for Boundary-scan and programming.
Figure 24-2. TAP Controller State Diagram 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR Shift-IR 0 1 1 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 24.4 1 Exit1-IR 0 1 0 1 Exit1-DR 0 1 Update-IR 0 1 0 TAP Controller The TAP controller is a 16-state finite state machine that controls the operation of the Boundary-scan circuitry, JTAG programming circuitry, or On-chip Debug system.
TDO pin. The JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls the circuitry surrounding the selected Data Register. • Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift Register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine.
The JTAGEN Fuse must be programmed to enable the JTAG Test Access Port. In addition, the OCDEN Fuse must be programmed and no Lock bits must be set for the On-chip Debug system to work. As a security feature, the Onchip Debug system is disabled when any Lock bits are set. Otherwise, the On-chip Debug system would have provided a back-door into a secured device. The AVR JTAG ICE from Atmel is a powerful development tool for On-chip Debugging of all AVR 8-bit RISC Microcontrollers with IEEE 1149.
The details on programming through the JTAG interface and programming specific JTAG instructions are given in the section “Programming via the JTAG Interface” on page 284. 24.9 24.9.1 Register Description OCDR – On-chip Debug Register Bit 7 6 5 4 3 2 1 0 MSB/IDRD LSB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 OCDR The OCDR Register provides a communication channel from the running program in the microcontroller to the debugger.
25. IEEE 1149.1 (JTAG) Boundary-scan 25.1 Features • • • • • 25.2 JTAG (IEEE std. 1149.
25.3.1 Bypass Register The Bypass Register consists of a single Shift Register stage. When the Bypass Register is selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass Register can be used to shorten the scan chain on a system when the other devices are to be tested. 25.3.2 Device Identification Register Figure 24-1 shows the structure of the Device Identification Register. Figure 25-1.
Figure 25-2. Reset Register To TDO From other Internal and External Reset Sources From TDI D Q Internal Reset ClockDR · AVR_RESET 25.3.4 Boundary-scan Chain The Boundary-scan Chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as the boundary between digital and analog logic for analog circuitry having Off-chip connections. See “Boundary-scan Chain” on page 236 for a complete description. 25.
25.4.3 SAMPLE_PRELOAD; $2 Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan Chain is selected as Data Register. The active states are: • Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain. • Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
Figure 25-3. Boundary-scan Cell for Bidirectional Port Pin with Pull-up Function.
Figure 25-4. General Port Pin Schematic Diagram(1) PUExn PUD Q D DDxn Q CLR RESET OCxn WDx Q Pxn ODxn D PORTxn Q CLR WPx IDxn DATA BUS RDx RESET RRx SLEEP SYNCHRONIZER D Q L Q D RPx Q PINxn Q CLK I/O PUD: PUExn: OCxn: ODxn: IDxn: SLEEP: Note: 25.5.
Figure 25-5. Additional Scan Signal for the Two-wire Interface PUExn OCxn ODxn TWIEN Pxn SRC Slew-rate Limited IDxn 25.5.3 Scanning the RESET Pin The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high logic for High Voltage Parallel Programming. An observe-only cell as shown in Figure 24-6 is inserted both for the 5V reset signal; RSTT, and the 12V reset signal; RSTHV. Figure 25-6.
Figure 25-7. Boundary-scan Cells for Oscillators and Clock Options To Next Cell ShiftDR XTAL2/TOSC2 Oscillator EXTEST To Next Cell ShiftDR 0 ENABLE OUTPUT 1 FF1 0 D Q D Q 0 1 D G From Previous Cell ClockDR To System Logic From Digital Logic XTAL1/TOSC1 Q 1 UpdateDR From Previous Cell ClockDR Table 24-3 summaries the scan registers for the external clock pin XTAL1, Oscillators with XTAL1/XTAL2 connections as well as 32kHz Timer Oscillator. Table 25-3.
Figure 25-8. Analog Comparator BANDGAP REFERENCE ACBG ACO AC_IDLE ACME ADCEN ADC MULTIPLEXER OUTPUT Figure 25-9.
Table 25-4. Boundary-scan Signals for the Analog Comparator Signal Name Direction as Seen from the Comparator AC_IDLE Input Turns off Analog comparator when true ACO Output Analog Comparator Output ACME Input Uses output signal from ADC mux when true 0 Depends upon µC code being executed ACBG Input Bandgap Reference enable 0 Depends upon µC code being executed 25.5.
Table 25-5.
Table 25-5.
If the ADC is not to be used during scan, the recommended input values from Table 24-5 should be used. The user is recommended not to use the Differential Gain stages during scan. Switch-cap based gain stages require fast operation and accurate timing which is difficult to obtain when used in a scan chain. Details concerning operations of the differential gain stage is therefore not provided.
Table 25-6. Step Algorithm for Using the ADC Actions ADCEN DAC MUXEN HOLD PRECH PA3. Data PA3. Control PA3.
Table 25-7.
Table 25-7. ATmega32A Boundary-scan Order (Continued) Bit Number Signal Name Module 112 MUXEN_7 ADC 111 MUXEN_6 110 MUXEN_5 109 MUXEN_4 108 MUXEN_3 107 MUXEN_2 106 MUXEN_1 105 MUXEN_0 104 NEGSEL_2 103 NEGSEL_1 102 NEGSEL_0 101 PASSEN 100 PRECH 99 SCTEST 98 ST 97 VCCREN 96 PB0.Data 95 PB0.Control 94 PB0.Pullup_Enable 93 PB1.Data 92 PB1.Control 91 PB1.Pullup_Enable 90 PB2.Data 89 PB2.Control 88 PB2.Pullup_Enable 87 PB3.Data 86 PB3.Control 85 PB3.
Table 25-7. ATmega32A Boundary-scan Order (Continued) Bit Number Signal Name Module 81 PB5.Data Port B 80 PB5.Control 79 PB5.Pullup_Enable 78 PB6.Data 77 PB6.Control 76 PB6.Pullup_Enable 75 PB7.Data 74 PB7.Control 73 PB7.Pullup_Enable 72 RSTT 71 RSTHV Reset Logic (Observe-Only) 70 EXTCLKEN Enable signals for main clock/Oscillators 69 OSCON 68 RCOSCEN 67 OSC32EN 66 EXTCLK (XTAL1) 65 OSCCK 64 RCCK 63 OSC32CK 62 TWIEN TWI 61 PD0.Data Port D 60 PD0.
Table 25-7. ATmega32A Boundary-scan Order (Continued) Bit Number Signal Name Module 46 PD5.Data Port D 45 PD5.Control 44 PD5.Pullup_Enable 43 PD6.Data 42 PD6.Control 41 PD6.Pullup_Enable 40 PD7.Data 39 PD7.Control 38 PD7.Pullup_Enable 37 PC0.Data 36 PC0.Control 35 PC0.Pullup_Enable 34 PC1.Data 33 PC1.Control 32 PC1.Pullup_Enable 31 PC6.Data 30 PC6.Control 29 PC6.Pullup_Enable 28 PC7.Data 27 PC7.Control 26 PC7.Pullup_Enable 25 TOSC 24 TOSCON 23 PA7.
Table 25-7. Bit Number Signal Name Module 11 PA3.Data Port A 10 PA3.Control 9 PA3.Pullup_Enable 8 PA2.Data 7 PA2.Control 6 PA2.Pullup_Enable 5 PA1.Data 4 PA1.Control 3 PA1.Pullup_Enable 2 PA0.Data 1 PA0.Control 0 Notes: 25.7 ATmega32A Boundary-scan Order (Continued) PA0.Pullup_Enable 1. PRIVATE_SIGNAL1 should always be scanned in as zero. 2. PRIVATE_SIGNAL2 should always be scanned in as zero.
26. Boot Loader Support – Read-While-Write Self-Programming 26.1 Features • • • • • • • Read-While-Write Self-Programming Flexible Boot Memory size High Security (Separate Boot Lock Bits for a Flexible Protection) Separate Fuse to Select Reset Vector Optimized Page(1) Size Code Efficient Algorithm Efficient Read-Modify-Write Support Note: 26.2 1. A page is a section in the flash consisting of several bytes (see Table 26-5 on page 269) used during programming.
• When erasing or writing a page located inside the RWW section, the NRWW section can be read during the operation. • When erasing or writing a page located inside the NRWW section, the CPU is halted during the entire operation. Note that the user software can never read any code that is located inside the RWW section during a Boot Loader software operation.
Figure 26-1. Read-While-Write vs.
Figure 26-2.
Table 26-2. BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing the Application section. 2 1 0 SPM is not allowed to write to the Application section. 0 SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If interrupt vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
Table 26-4. BOOTRST Note: 26.7 Boot Reset Fuse(1) Reset Address 1 Reset Vector = Application reset (address $0000) 0 Reset Vector = Boot Loader reset (see Table 25-6 on page 263) 1. “1” means unprogrammed, “0” means programmed Addressing the Flash during Self-Programming The Z-pointer is used to address the SPM commands.
26.8 Self-Programming the Flash The program memory is updated in a page by page fashion. Before programming a page with the data stored in the temporary page buffer, the page must be erased.
26.8.4 Using the SPM Interrupt If the SPM interrupt is enabled, the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCR is cleared. This means that the interrupt can be used instead of polling the SPMCR Register in software. When using the SPM interrupt, the Interrupt Vectors should be moved to the BLS section to avoid that an interrupt is accessing the RWW section when it is blocked for reading. How to move the interrupts is described in “Interrupts” on page 45. 26.8.
instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU cycles. When BLBSET and SPMEN are cleared, LPM will work as described in the Instruction set Manual. Bit 7 6 5 4 3 2 1 0 Rd – – BLB12 BLB11 BLB02 BLB01 LB2 LB1 The algorithm for reading the Fuse Low bits is similar to the one described above for reading the Lock bits. To read the Fuse Low bits, load the Z-pointer with $0000 and set the BLBSET and SPMEN bits in SPMCR.
26.8.12 Simple Assembly Code Example for a Boot Loader ;-the routine writes one page of data from RAM to Flash ; the first data location in RAM is pointed to by the Y pointer ; the first data location in Flash is pointed to by the Z pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the Do_spm sub routine). Only code inside NRWW section can ; be read during self-programming (page erase and page write).
; return to RWW section ; verify that RWW section is safe to read Return: in temp1, SPMCR sbrs temp1, RWWSB ; If RWWSB is set, the RWW section is not ; ready yet ret ; re-enable the RWW section ldi spmcrval, (1<
Note: 1. For details about these two section, see “NRWW – No Read-While-Write Section” on page 253 and “RWW – ReadWhile-Write Section” on page 253 Table 26-8. Explanation of Different Variables used in Figure 25-3 and the Mapping to the Z-pointer Corresponding Z-value(1) Variable PCMSB Description 13 Most significant bit in the Program Counter.
When programming (Page Erase or Page Write) to the RWW section, the RWW section is blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the user software must wait until the programming is completed (SPMEN will be cleared). Then, if the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction within four clock cycles re-enables the RWW section.
27. Memory Programming 27.1 Program And Data Memory Lock Bits The ATmega32A provides six Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 26-2. The Lock bits can only be erased to “1” with the Chip Erase command. Table 27-1.
Table 27-2. Lock Bit Protection Modes (Continued) Memory Lock Bits(2) 1 1 1 No restrictions for SPM or LPM accessing the Boot Loader section. 2 1 0 SPM is not allowed to write to the Boot Loader section. 0 SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If interrupt vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
Table 27-4. Fuse Low Byte Fuse Low Byte Bit No.
27.5 Page Size Table 27-5. No. of Words in a Page and no. of Pages in the Flash Flash Size 16K words (32Kbytes) Table 27-6. 27.6 Page Size PCWORD No. of Pages PCPAGE PCMSB 64 words PC[5:0] 256 PC[13:6] 13 No. of Words in a Page and no. of Pages in the EEPROM EEPROM Size Page Size PCWORD No.
Table 27-7.
Table 27-10. Command Byte Bit Coding (Continued) Command Byte Command Executed 0000 0100 Read Fuse and Lock bits 0000 0010 Read Flash 0000 0011 Read EEPROM 27.7 Parallel Programming 27.7.1 Enter Programming Mode The following algorithm puts the device in Parallel Programming mode: 1. Apply 4.5V - 5.5V between VCC and GND, and wait at least 100 µs. 2. Set RESET to “0” and toggle XTAL1 at least 6 times 3. Set the Prog_enable pins listed in Table 26-8 on page 270 to “0000” and wait at least 100 ns.
6. Wait until RDY/BSY goes high before loading a new command. 27.7.4 Programming the Flash The Flash is organized in pages, see Table 26-5 on page 269. When programming the Flash, the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”.
J. End Page Programming 1. 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set DATA to “0000 0000”. This is the command for No Operation. 3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are reset. Figure 27-2. Addressing the Flash which is Organized in Pages PCMSB PROGRAM COUNTER PAGEMSB PCPAGE PCWORD PAGE ADDRESS WITHIN THE FLASH WORD ADDRESS WITHIN A PAGE PROGRAM MEMORY PAGE PAGE PCWORD[PAGEMSB:0]: 00 INSTRUCTION WORD 01 02 PAGEEND Note: 1.
27.7.5 Programming the EEPROM The EEPROM is organized in pages, see Table 26-6 on page 269. When programming the EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to “Programming the Flash” on page 272 for details on Command, Address and Data loading): 1. A: Load Command “0001 0001”. 2. G: Load Address High Byte ($00 - $FF) 3. B: Load Address Low Byte ($00 - $FF) 4.
6. Set OE to “1”. 27.7.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash” on page 272 for details on Command and Address loading): 1. A: Load Command “0000 0011”. 2. G: Load Address High Byte ($00 - $FF) 3. B: Load Address Low Byte ($00 - $FF) 4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA. 5. Set OE to “1”. 27.7.
Figure 27-5. Programming the Fuses Write Fuse Low byte DATA A C $40 DATA XX Write Fuse high byte A C $40 DATA XX XA1 XA0 BS1 BS2 XTAL1 WR RDY/BSY RESET +12V OE PAGEL 27.7.10 Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on page 272 for details on Command and Data loading): 1. A: Load Command “0010 0000”. 2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. 3.
Figure 27-6. Mapping between BS1, BS2 and the Fuse- and Lock Bits during Read 0 Fuse Low Byte DATA Lock Bits 0 1 BS1 Fuse High Byte 1 BS2 27.7.12 Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on page 272 for details on Command and Address loading): 1. A: Load Command “0000 1000”. 2. B: Load Address Low Byte ($00 - $02). 3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA. 4. Set OE to “1”.
Figure 27-8. Parallel Programming Timing, Loading Sequence with Timing Requirements(1) LOAD ADDRESS (LOW BYTE) LOAD DATA LOAD DATA (HIGH BYTE) LOAD DATA (LOW BYTE) tXLPH t XLXH LOAD ADDRESS (LOW BYTE) tPLXH XTAL1 BS1 PAGEL DATA ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte) XA0 XA1 Note: 1. The timing requirements shown in Figure 26-7 (that is, tDVXH, tXHXL, and tXLDX) also apply to loading operation. Figure 27-9.
Table 27-11. Parallel Programming Characteristics, VCC = 5V ±10% (Continued) Symbol Parameter Min tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2/1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns tWLRL WR Low to RDY/BSY Low tWLRH WR Low to RDY/BSY High(1) Units 1 s 3.7 4.5 ms 7.
Figure 27-10. SPI Serial Programming and Verify(1) +2.7 - 5.5V VCC +2.7 - 5.5V(2) MOSI PB5 MISO PB6 SCK PB7 AVCC XTAL1 RESET GND Notes: 1. If the device is clocked by the Internal Oscillator, it is no need to connect a clock source to the XTAL1 pin. 2. VCC -0.3V < AVCC < VCC +0.3V, however, AVCC should always be within 2.7V - 5.
loaded before data high byte is applied for a given address. The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address. If polling is not used, the user must wait at least tWD_FLASH before issuing the next page. (See Table 26-13). Accessing the SPI Serial Programming interface before the Flash write operation completes can result in incorrect programming. 5.
Figure 27-11.
Table 27-14. SPI Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Read Program Memory Byte 1 Byte 2 Byte 3 Byte4 Operation 1010 1100 0101 0011 xxxx xxxx xxxx xxxx Enable SPI Serial Programming after RESET goes low. 1010 1100 100x xxxx xxxx xxxx xxxx xxxx Chip Erase EEPROM and Flash. 0010 H000 00aa aaaa bbbb bbbb oooo oooo Read H (high or low) data o from Program memory at word address a:b.
27.10 Programming via the JTAG Interface Programming through the JTAG interface requires control of the four JTAG specific pins: TCK, TMS, TDI and TDO. Control of the reset and clock pins is not required. To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR must be cleared. Alternatively, if the JTD bit is set, the External Reset can be forced low.
Figure 27-12. State Machine Sequence for Changing the Instruction Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR 0 Shift-IR 1 1 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 27.10.2 1 Exit1-IR 0 1 0 1 Exit1-DR 0 1 Update-IR 0 1 0 AVR_RESET ($C) The AVR specific public JTAG instruction for setting the AVR device in the Reset mode or taking the device out from the Reset Mode.
27.10.4 PROG_COMMANDS ($5) The AVR specific public JTAG instruction for entering programming commands via the JTAG port. The 15-bit Programming Command Register is selected as Data Register. The active states are the following: • Capture-DR: The result of the previous command is loaded into the Data Register. • Shift-DR: The Data Register is shifted by the TCK input, shifting out the result of the previous command and shifting in the new command.
The output from this Data Register is not latched, so the reset will take place immediately, as shown in Figure 24-2 on page 235. 27.10.9 Programming Enable Register The Programming Enable Register is a 16-bit register. The contents of this register is compared to the programming enable signature, binary code 1010_0011_0111_0000. When the contents of the register is equal to the programming enable signature, programming via the JTAG port is enabled.
Figure 27-14. Programming Command Register TDI S T R O B E S A D D R E S S / D A T A Flash EEPROM Fuses Lock Bits TDO Figure 27-15. JTAG Programming Instruction Set a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 1a. Chip erase 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx 1b.
Figure 27-15. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence 3c. Load Address Low Byte 0000011_bbbbbbbb xxxxxxx_xxxxxxxx 3d. Read Data Low and High Byte 0110010_00000000 0110110_00000000 0110111_00000000 xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo 4a. Enter EEPROM Write 0100011_00010001 xxxxxxx_xxxxxxxx 4b.
Figure 27-15. JTAG Programming Instruction Set (Continued) a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care Instruction TDI sequence TDO sequence Notes 7c. Write Lock Bits 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (1) 7d. Poll for Lock Bit Write complete 0110011_00000000 xxxxxox_xxxxxxxx (2) 8a.
Figure 27-16. State Machine Sequence for Changing/Reading the Data Word 1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 1 Select-IR Scan 0 1 0 1 Capture-DR Capture-IR 0 0 Shift-DR 0 Shift-IR 1 1 1 Exit1-IR 0 0 Pause-DR 0 0 Pause-IR 1 1 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 0 1 Exit1-DR 0 1 Update-IR 0 1 0 27.10.11 Virtual Flash Page Load Register The Virtual Flash Page Load Register is a virtual scan chain with length equal to the number of bits in one Flash page.
Figure 27-17. Virtual Flash Page Load Register STROBES TDI State Machine ADDRESS Flash EEPROM Fuses Lock Bits D A T A TDO 27.10.12 Virtual Flash Page Read Register The Virtual Flash Page Read Register is a virtual scan chain with length equal to the number of bits in one Flash page plus 8. Internally the Shift Register is 8-bit, and the data are automatically transferred from the Flash data page byte by byte.
27.10.14 Entering Programming Mode 1. Enter JTAG instruction AVR_RESET and shift 1 in the Reset Register. 2. Enter instruction PROG_ENABLE and shift 1010_0011_0111_0000 in the Programming Enable Register. 27.10.15 Leaving Programming Mode 1. Enter JTAG instruction PROG_COMMANDS. 2. Disable all programming instructions by usning no operation instruction 11a. 3. Enter instruction PROG_ENABLE and shift 0000_0000_0000_0000 in the programming Enable Register. 4.
4. Read data using programming instruction 3d. 5. Repeat steps 3 and 4 until all data have been read. A more efficient data transfer can be achieved using the PROG_PAGEREAD instruction: 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Flash read using programming instruction 3a. 3. Load the page address using programming instructions 3b and 3c. PCWORD (refer to Table 26-5 on page 269) is used to address within one page and must be written as 0. 4. Enter JTAG instruction PROG_PAGEREAD. 5.
7. Write Fuse low byte using programming instruction 6f. 8. Poll for Fuse write complete using programming instruction 6g, or wait for tWLRH (refer to Table 26-11 on page 279). 27.10.22 Programming the Lock Bits 1. Enter JTAG instruction PROG_COMMANDS. 2. Enable Lock bit write using programming instruction 7a. 3. Load data using programming instructions 7b. A bit value of “0” will program the corresponding Lock bit, a “1” will leave the Lock bit unchanged. 4.
28. Electrical Characteristics 28.1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0.5V to VCC+0.5V Voltage on RESET with respect to Ground......-0.5V to +13.0V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
TA = -40C to 85C, VCC = 2.7 V to 5.5 V (Unless Otherwise Noted) Symbol Parameter Power Supply Current ICC Power-down Mode(5) Condition Typ Max Units Active 1MHz, VCC = 3V 0.6 Active 4MHz, VCC = 3V 2.1 5 mA Active 8MHz, VCC = 5V 7.5 15 mA Idle 1MHz, VCC = 3V 0.2 Idle 4MHz, VCC = 3V 0.6 2.5 mA Idle 8MHz, VCC = 5V 2.
28.3 Speed Grades Figure 28-1. Maximum Frequency vs. VCC. 16 MHz 8 MHz Safe Operating Area 2.7V 28.4 28.4.1 4.5V 5.5V Clock Characteristics External Clock Drive Waveforms Figure 28-2. External Clock Drive Waveforms V IH1 V IL1 28.4.2 External Clock Drive Figure 28-3. External Clock Drive VCC = 2.7V to 5.5V VCC = 4.5V to 5.5V Min Max Min Max Units 0 8 0 16 MHz Symbol Parameter 1/tCLCL Oscillator Frequency tCLCL Clock Period 125 62.
Figure 28-4. External RC Oscillator, Typical Frequencies (VCC = 5V) Notes: R [k](1) C [pF] f(2) 33 22 650kHz 10 22 2.0MHz 1. R should be in the range 3 k - 100 k, and C should be at least 20 pF. The C values given in the table includes pin capacitance. This will vary with package type. 2. The frequency will vary with package type and board layout. 28.5 System and Reset Characteristics Table 28-1.
Timing symbols refer to Figure 27-5. Table 28-2. Two-wire Serial Bus Requirements Symbol Parameter VIL VIH Vhys (1) VOL(1) Min Max Units Input Low-voltage -0.5 0.3 VCC V Input High-voltage 0.7 VCC VCC + 0.
Figure 28-5. Two-wire Serial Bus Timing tof tHIGH tLOW tr tLOW SCL tSU;STA tHD;STA tHD;DAT tSU;DAT tSU;STO SDA tBUF 28.7 SPI Timing Characteristics See Figure 27-6 and Figure 27-7 for details. Table 28-3. SPI Timing Parameters Description Mode Min Typ Max 1 SCK period Master See Table 18-4 2 SCK high/low Master 50% duty cycle 3 Rise/Fall time Master 3.6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 0.
Figure 28-6. SPI Interface Timing Requirements (Master Mode) SS 6 1 SCK (CPOL = 0) 2 2 SCK (CPOL = 1) 4 MISO (Data Input) 5 3 MSB ... LSB 7 MOSI (Data Output) MSB 8 ... LSB Figure 28-7. SPI Interface Timing Requirements (Slave Mode) 18 SS 10 9 16 SCK (CPOL = 0) 11 11 SCK (CPOL = 1) 13 MOSI (Data Input) 14 12 MSB ... LSB 15 MISO (Data Output) MSB 17 ...
28.8 ADC Characteristics Table 28-4. Symbol ADC Characteristics, Single Ended channels, TA = -40C to 85C Parameter Condition Resolution Single Ended Conversion 10 Bits Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz 1.5 LSB Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 1MHz 3 LSB Single Ended Conversion VREF = 4V, VCC = 4V ADC clock = 200kHz Noise Reduction mode 1.
Table 28-5.
Table 28-5. ADC Characteristics, Differential channels, TA = -40C to 85C (Continued) Symbol Parameter VINT Internal Voltage Reference RREF Reference Input Resistance 32 k RAIN Analog Input Resistance 100 M Notes: Condition Min Typ Max Units 2.3 2.56 2.7 V 1. Minimum for AVCC is 2.7V. 2. Maximum for AVCC is 5.5V.
29. Typical Characteristics The following charts show typical behavior. These figures are not tested during manufacturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A square wave generator with rail-to-rail output is used as clock source. The power consumption in Power-down mode is independent of clock selection.
Figure 29-2. Active Supply Current vs. Frequency (1 - 16MHz) ICC (mA) 18 16 5.5V 14 5.0V 12 4.5V 10 4.0V 8 3.6V 6 3.3V 4 2.7V 2 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) RC Oscillator, 8MHz) Figure 29-3. Active Supply Current vs. VCC (Internal , 12 25 °C 10 85 °C -40 °C ICC (mA) 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-4. Active Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 6 25 °C 85 °C 5 -40 °C ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-5. Active Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 1.6 25 °C 85 °C 1.4 -40 °C 1.2 ICC (mA) 1 0.8 0.6 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-6. Active Supply Current vs. VCC (External Oscillator, 32kHz) 160 25 °C 140 120 ICC (uA) 100 80 60 40 20 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Idle Supply Current Figure 29-7. Idle Supply Current vs. Low Frequency (0.1 - 1.0MHz) 0.7 0.6 5.5 V 0.5 ICC (mA) 29.2 5.0 V 0.4 4.5 V 4.0 V 3.6 V 3.3 V 0.3 0.2 2.7 V 0.1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.
Figure 29-8. Idle Supply Current vs. Frequency (1 MHz - 16 MHz) 8 7 5.5V 6 5.0V ICC (mA) 5 4.5V 4 4.0V 3 3.6V 2 2.7V 1 3.3V 0 0 2 4 6 8 10 12 14 16 Frequency (MHz) Figure 29-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz) 5 -40 °C 25 °C 85 °C ICC (mA) 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 4MHz) 2.5 -40 °C 25 °C 85 °C ICC (mA) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-11. Idle Supply Current vs. VCC (Internal RC Oscillator, 1MHz) 0.8 0.7 85 °C 0.6 25 °C -40 °C ICC (mA) 0.5 0.4 0.3 0.2 0.1 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-12. Idle Supply Current vs. VCC (External Oscillator, 32kHz) 40 35 25 °C 30 ICC (uA) 25 20 15 10 5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-down Supply Current Figure 29-13. Power-down Supply Current vs. VCC (Watchdog Timer Disabled) 2 1.6 85 °C -40 °C 1.2 ICC (uA) 29.3 25 °C 0.8 0.4 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-14. Power-down Supply Current vs. VCC (Watchdog Timer Enabled) 20 85 °C -40 °C 25 °C 16 ICC (uA) 12 8 4 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Power-save Supply Current Figure 29-15. Power-save Supply Current vs. VCC (Watchdog Timer Disabled) 20 25 °C 16 12 ICC (uA) 29.4 8 4 0 2.5 3 3.5 4 4.5 5 5.
29.5 Standby Supply Current Figure 29-16. Standby Supply Current vs. VCC (WDT Disabled) 0.16 6MHz_xtal 6MHz_res 0.14 0.12 4MHz_res 4MHz_xtal ICC (mA) 0.1 0.08 2MHz_res 2MHz_xtal 450kHz_res 1MHz_res 0.06 0.04 0.02 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Pin Pull-up Figure 29-17. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V) 140 120 25 °C 100 85 °C IOP (uA) 29.
Figure 29-18. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V) 70 25 °C -40 °C 60 85 °C IOP (uA) 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 VOP (V) Figure 29-19. Reset Pull-up Resistor Current vs.
Figure 29-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V) 60 50 IRESET (uA) 40 30 20 10 -40 °C 0 25 °C 85 °C 0 0.5 1 1.5 2 2.5 3 VRESET(V) Pin Driver Strength Figure 29-21. I/O Pin Source Current vs. Output Voltage (VCC = 5V) 80 70 25 °C 60 -40 °C 85 °C 50 IOH (mA) 29.7 40 30 20 10 0 3 3.4 3.8 4.2 4.
Figure 29-22. I/O Pin Source Current vs. Output Voltage (VCC = 3V) 35 -40 °C 25 °C 30 85 °C IOH (mA) 25 20 15 10 5 0 1 1.5 2 2.5 3 VOH (V) Figure 29-23. I/O Pin Sink Current vs. Output Voltage (VCC = 5V) 90 -40 °C 80 25 °C 70 85 °C IOL (mA) 60 50 40 30 20 10 0 0 0.5 1 1.
Figure 29-24. I/O Pin Sink Current vs. Output Voltage (VCC = 3V) IOL (mA) 45 40 -40 °C 35 25 °C 30 85 °C 25 20 15 10 5 0 0 0.5 1 1.5 2 VOL (V) Pin Thresholds and Hysteresis Figure 29-25. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as “1”) 3 85 °C 25 °C 2.5 -40 °C 2 Threshold (V) 29.8 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-26. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as “0”) 2.5 85 °C 2 -40 °C Threshold (V) 25 °C 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-27. I/O Pin Input Hysteresis vs. VCC 0.6 -40 °C 25 °C Input Hysteresis (mV) 85 °C 0.4 0.2 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-28. Reset Input Threshold Voltage vs. VCC (VIH,Reset Pin Read as “1”) 2.5 2 Threshold (V) -40 °C 1.5 25 °C 85 °C 1 0.5 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-29. Reset Input Threshold Voltage vs. VCC (VIL,Reset Pin Read as “0”) 2.5 85 °C 25 °C -40 °C Threshold (V) 2 1.5 1 0.5 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-30. Reset Input Pin Hysteresis vs. VCC 0.5 Input Hysteresis (mV) 0.4 0.3 -40 °C 0.2 25 °C 0.1 85 °C 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) BOD Thresholds and Analog Comparator Offset Figure 29-31. BOD Thresholds vs. Temperature (BOD Level is 4.0V) 4.1 Rising VCC 4 Threshold (V) 29.9 3.9 Falling VCC 3.
Figure 29-32. BOD Thresholds vs. Temperature (BOD Level is 2.7V) 2.9 Rising VCC Threshold (V) 2.8 2.7 Falling VCC 2.6 -60 -40 -20 0 20 40 60 80 100 Temperature (C) Figure 29-33. Bandgap Voltage vs. VCC 1.25 1.248 Bandgap Voltage (V) 1.246 1.244 1.242 1.24 25 °C 1.238 85 °C 1.236 -40 °C 1.234 1.232 2.5 3 3.5 4 4.5 5 5.
29.10 Internal Oscillator Speed Figure 29-34. Watchdog Oscillator Frequency vs. VCC 1320 -40 °C 25 °C 1300 1280 85 °C F RC (kHz) 1260 1240 1220 1200 1180 1160 1140 1120 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-35. Calibrated 8MHz RC Oscillator Frequency vs. Temperature 8.5 8.3 8.1 F RC (MHz) 7.9 5.5 V 5.0 V 4.5 V 4.0 V 7.7 7.5 7.3 3.6 V 3.3 V 7.1 6.9 2.7 V 6.7 6.
Figure 29-36. Calibrated 8MHz RC Oscillator Frequency vs. VCC 9 8.5 -40 °C 25 °C F RC (MHz) 8 85 °C 7.5 7 6.5 6 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-37. Calibrated 8MHz RC Oscillator Frequency vs.
Figure 29-38. Calibrated 4MHz RC Oscillator Frequency vs. Temperature 4.2 4.1 F RC (MHz) 4 5.5 V 5.0 V 4.5 V 4.0 V 3.9 3.8 3.6 V 3.3 V 3.7 2.7 V 3.6 3.5 -60 -40 -20 0 20 40 60 80 100 Temperature Figure 29-39. Calibrated 4MHz RC Oscillator Frequency vs. VCC 4.2 4.1 -40 °C 25 °C F RC (MHz) 4 85 °C 3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 4.5 5 5.
Figure 29-40. Calibrated 4MHz RC Oscillator Frequency vs. Osccal Value 8 7 -40 °C 25 °C 6 85 °C F RC (MHz) 5 4 3 2 1 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) Figure 29-41. Calibrated 2MHz RC Oscillator Frequency vs. Temperature 2.1 2.05 F RC (MHz) 2 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 1.95 1.9 1.85 2.7 V 1.
Figure 29-42. Calibrated 2MHz RC Oscillator Frequency vs. VCC 2.1 -40 °C 25 °C 2 F RC (MHz) 85 °C 1.9 1.8 1.7 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-43. Calibrated 2MHz RC Oscillator Frequency vs. Osccal Value 4 -40 °C 3.5 25 °C 85 °C 3 F RC (MHz) 2.5 2 1.5 1 0.
Figure 29-44. Calibrated 1MHz RC Oscillator Frequency vs. Temperature 1.04 1.02 F RC (MHz) 1 5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 0.98 0.96 0.94 2.7 V 0.92 -60 -40 -20 0 20 40 60 80 100 Temperature Figure 29-45. Calibrated 1MHz RC Oscillator Frequency vs. VCC 1.04 1.02 -40 °C 25 °C F RC (MHz) 1 85 °C 0.98 0.96 0.94 0.92 2.5 3 3.5 4 4.5 5 5.
Figure 29-46. Calibrated 1MHz RC Oscillator Frequency vs. Osccal Value 2 -40 °C 25 °C 85 °C 1,8 1,6 F RC (MHz) 1,4 1,2 1 0,8 0,6 0,4 0,2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 OSCCAL (X1) 29.11 Current Consumption of Peripheral Units Figure 29-47. Brownout Detector Current vs. VCC 20 -40 °C 25 °C 18 16 85 °C 14 ICC (uA) 12 10 8 6 4 2 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-48. ADC Current vs. VCC (AREF = AVCC) 350 85 °C 25 °C 300 -40 °C ICC (uA) 250 200 150 100 50 0 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-49. AREF External Reference Current vs. VCC 200 85 °C 25 °C -40 °C ICC (uA) 150 100 50 0 2.5 3 3.5 4 4.5 5 5.
Figure 29-50. Analog Comparator Current vs. VCC 100 90 80 85 °C ICC (uA) 70 25 °C -40 °C 60 50 40 30 20 2.5 3 3.5 4 4.5 5 5.5 VCC (V) Figure 29-51. Programming Current vs. VCC 9 8 -40 °C 7 25 °C 6 ICC (mA) 85 °C 5 4 3 2 1 0 2.5 3 3.5 4 4.5 5 5.
29.12 Current Consumption in Reset and Reset Pulsewidth Figure 29-52. Reset Supply Current vs. Low Frequency (0.1 - 1.0MHz, Excluding Current Through The Reset Pull-up) 3 2.5 5.5 V 5.0 V ICC (mA) 2 4.5 V 1.5 4.0 V 3.6 V 3.3 V 1 2.7 V 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz) Figure 29-53. Reset Supply Current vs. Frequency (1 - 16MHz, Excluding Current Through The Reset Pull-up) 16 5.5V 14 5.0V 12 4.5V ICC (mA) 10 4.0V 8 3.6V 6 3.3V 4 2.
Figure 29-54. Minimum Reset Pulse Width vs. VCC 800 700 Pulsewidth (ns) 600 500 400 85 °C 25 °C -40 °C 300 200 100 0 2.5 3 3.5 4 4.5 5 5.
30.
Notes: 1. When the OCDEN Fuse is unprogrammed, the OSCCAL Register is always accessed on this address. Refer to the debugger specific documentation for details on how to use the OCDR Register. 2. Refer to the USART description for details on how to access UBRRH and UCSRC. 3. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 4. Some of the Status Flags are cleared by writing a logical one to them.
31.
Mnemonics Operands Description Operation Flags BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC PC + k + 1 None #Clocks 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC PC + k + 1 None 1/2 None 1 None 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word Rd Rr Rd+1:Rd Rr+1:Rr LDI Rd, K Load Immediate Rd K None 1 LD Rd,
Mnemonics Operands MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK Description Operation Flags #Clocks No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr.
32. Ordering Information Speed (MHz) 16 Notes: Power Supply 2.7V - 5.5V Ordering Code(2) Package(1) ATmega32A-AU SATmega32A-AUR(3) ATmega32A-PU ATmega32A-MU ATmega32A-MUR(3) 44A 44A 40P6 44M1 44M1 Industrial (-40oC to 85oC) ATmega32A-AN ATmega32A-ANR(3) ATmega32A-MN ATmega32A-MNR(3) 44A 44A 44M1 44M1 Extended (-40oC to 105oC)(4) Operational Range 1. This device can also be supplied in wafer form.
33. Packaging Information 33.1 44A PIN 1 IDENTIFIER PIN 1 e B E1 E D1 D C 0°~7° A1 A2 A L COMMON DIMENSIONS (Unit of Measure = mm) Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10mm maximum. SYMBOL MIN NOM MAX A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.
33.2 40P6 D PIN 1 E1 A SEATING PLANE A1 L B B1 e E 0º ~ 15º C COMMON DIMENSIONS (Unit of Measure = mm) REF eB Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). SYMBOL MIN NOM MAX A – – 4.826 A1 0.381 – – D 52.070 – 52.578 E 15.240 – 15.875 E1 13.462 – 13.970 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.
33.3 44M1 D Marked Pin# 1 ID E SEATING PLANE A1 TOP VIEW A3 A K L Pin #1 Corner D2 1 2 3 Option A SIDE VIEW Pin #1 Triangle E2 Option B K Option C b e Pin #1 Chamfer (C 0.30) Pin #1 Notch (0.20 R) BOTTOM VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX A 0.80 0.90 1.00 A1 – 0.02 0.05 A3 0.20 REF b 0.18 0.23 0.30 D 6.90 7.00 7.10 D2 5.00 5.20 5.40 E 6.90 7.00 7.10 E2 5.00 5.20 5.40 e Note: JEDEC Standard MO-220, Fig.
34. Errata 34.1 ATmega32A, rev. J to rev. K • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices.
34.2 ATmega32A, rev. G to rev. I • • • • First Analog Comparator conversion may be delayed Interrupts may be lost when writing the timer registers in the asynchronous timer IDCODE masks data from TDI input Reading EEPROM by using ST or STS to set EERE bit triggers unexpected interrupt request. 1. First Analog Comparator conversion may be delayed If the device is powered by a slow rising VCC, the first Analog Comparator conversion will take longer than expected on some devices.
35. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 35.1 35.2 Rev. 8155E – 02/2014 1. Updated the “Features” with “Capacitive touch sensing” capability. 2. Added “Errata” “ATmega32A, rev. J to rev. K” on page 325. Rev. 8155D – 10/2013 1. 35.3 35.4 35.5 Added nominal values for symbol B, C and L in the TQFP-44 package drawing, “44A” on page 322.
ATmega32A [DATASHEET] Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014 328
Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 3 2.1 Block Diagram ...................................................................................................3 2.2 Pin Descriptions ...............
9.8 External Clock .................................................................................................28 9.9 Timer/Counter Oscillator ..................................................................................29 9.10 Register Description ........................................................................................30 10 Power Management and Sleep Modes ................................................. 31 10.1 Sleep Modes .................................................
15.6 Compare Match Output Unit ............................................................................71 15.7 Modes of Operation .........................................................................................72 15.8 Timer/Counter Timing Diagrams ......................................................................76 15.9 Register Description ........................................................................................78 16 Timer/Counter0 and Timer/Counter1 Prescalers .....
19.2 Overview ........................................................................................................128 19.3 SS Pin Functionality ......................................................................................132 19.4 Data Modes ...................................................................................................134 20 USART ................................................................................................... 136 20.1 Features .....................
23.5 Prescaling and Conversion Timing ................................................................196 23.6 Changing Channel or Reference Selection ...................................................199 23.7 ADC Noise Canceler .....................................................................................200 23.8 ADC Conversion Result .................................................................................203 23.9 Register Description ..............................................
27 Memory Programming ......................................................................... 248 27.1 Program And Data Memory Lock Bits ...........................................................248 27.2 Fuse Bits ........................................................................................................249 27.3 Signature Bytes .............................................................................................250 27.4 Calibration Byte ........................................
32 Ordering Information ........................................................................... 321 33 Packaging Information ......................................................................... 322 33.1 44A ................................................................................................................322 33.2 40P6 ..............................................................................................................323 33.3 44M1 .........................................
XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2014 Atmel Corporation. / Rev.: Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014. Atmel®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. DISCLAIMER: The information in this document is provided in connection with Atmel products.
