Datasheet

119
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC2 pin. Setting the
COM21:0 bits to 2 will produce a non-inverted PWM. An inverted PWM output can be generated by setting the
COM21:0 to 3 (see Table 17-5 on page 134). The actual OC2 value will only be visible on the port pin if the data
direction for the port pin is set as output. The PWM waveform is generated by clearing (or setting) the OC2 Regis-
ter at the compare match between OCR2 and TCNT2 when the counter increments, and setting (or clearing) the
OC2 Register at compare match between OCR2 and TCNT2 when the counter decrements. The PWM frequency
for the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR2 is set equal to BOTTOM, the output will be continuously low and if set
equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
At the very start of period 2 in Figure 17-7 OCn has a transition from high to low even though there is no Compare
Match. The point of this transition is to guarantee symmetry around BOTTOM. THere are two cases that give a
transition without Compare Match.
• OCR2A chages its value from MAX, like in Figure 17-7. When the OCR2A value is MAX the OCn pin value is
the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn
value at MAX must correspond to the result of an up-counting Compare Match.
• The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare
Match and hence the OCn change that would have happened on the way up.
18.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in Synchronous mode, and the timer clock (clk
T2
) is therefore shown
as a clock enable signal. In Asynchronous mode, clk
I/O
should be replaced by the Timer/Counter Oscillator clock.
The figures include information on when Interrupt Flags are set. Figure 17-8 contains timing data for basic
Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than
phase correct PWM mode.
Figure 18-8. Timer/Counter Timing Diagram, no Prescaling
Figure 17-9 shows the same timing data, but with the prescaler enabled.
f
OCnPCPWM
f
clk_I/O
N 510
------------------=
clk
Tn
(clk
I/O
/1)
TOVn
clk
I/O
TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1