Datasheet

69
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is
referred to as the timer clock (clk
T0
).
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The
result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on
the Output Compare Pin (OC0). See “Output Compare Unit” on page 75. for details. The compare match event will
also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request.
15.2.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise
form must be used, that is, TCNT0 for accessing Timer/Counter0 counter value and so on.
The definitions in Table 14-1 are also used extensively throughout the document.
15.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the
clock select logic which is controlled by the clock select (CS02:0) bits located in the Timer/Counter Control Regis-
ter (TCCR0). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on
page 88.
15.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 14-2 shows a
block diagram of the counter and its surroundings.
Figure 15-2. Counter Unit Block Diagram
Signal description (internal signals):
count Increment or decrement TCNT0 by 1.
direction Select between increment and decrement.
clear Clear TCNT0 (set all bits to zero).
clk
Tn
Timer/Counter clock, referred to as clk
T0
in the following.
Table 15-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes 0x00.
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0 Register. The assignment is dependent
on the mode of operation.
DATA BU S
TCNTn Control Logic
count
TOVn
(Int. Req.)
Clock Select
TOP
Tn
Edge
Detector
( From Prescaler )
clk
Tn
BOTTOM
direction
clear