Datasheet

68
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
15. 8-bit Timer/Counter0 with PWM
15.1 Features
• Single Compare Unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0)
15.2 Overview
Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. A simplified block diagram
of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual placement of I/O pins, refer to “Pinout
ATmega32A” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The
device-specific I/O Register and bit locations are listed in the “Register Description” on page 84.
Figure 15-1. 8-bit Timer/Counter Block Diagram
15.2.1 Registers
The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt request (abbrevi-
ated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR). All interrupts are
individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure
since these registers are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on the T0 pin. The
Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement)
Timer/Counter
DATA BU S
=
TCNTn
Waveform
Generation
OCn
= 0
Control Logic
= 0xFF
BOTTOM
count
clear
direction
TOVn
(Int.Req.)
OCRn
TCCRn
Clock Select
Tn
Edge
Detector
( From Prescaler )
clk
Tn
TOP
OCn
(Int.Req.)