Datasheet

31
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
10. Power Management and Sleep Modes
10.1 Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR
provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
Figure 8-1 on page 25 presents the different clock systems in the ATmega32A, and their distribution. The figure is
helpful in selecting an appropriate sleep mode. Table 10-1 shows the different clock options and their wake-up
sources.
Notes: 1. External Crystal or resonator selected as clock source.
2. If AS2 bit in ASSR is set.
3. Only INT2 or level interrupt INT1 and INT0.
To enter any of the six sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction
must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register select which sleep mode (Idle, ADC
Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP
instruction. See Table 10-2 on page 35 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the instruc-
tion following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from
sleep. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
10.2 Idle Mode
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU
but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Interface, Timer/Counters, Watchdog, and
the interrupt system to continue operating. This sleep mode basically halts clk
CPU
and clk
FLASH
, while allowing the
other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer
Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not
Table 10-1. Active Clock Domains and Wake Up Sources in the Different Sleep Modes
Active Clock domains Oscillators Wake-up Sources
Sleep Mode
clk
CPU
clk
FLASH
clk
IO
clk
ADC
clk
ASY
Main Clock Source Enabled Timer Oscillator Enabled INT2 INT1 INT0 TWI Address Match Timer 2 SPM / EEPROM Ready ADC Other I/O
Idle X X X X X
(2)
X XXXXX
ADC Noise
Reduction
XX X X
(2)
X
(3)
XXXX
Power-down X
(3)
X
Power-save X
(2)
X
(2)
X
(3)
XX
(2)
Standby
(1)
XX
(3)
X
Extended
Standby
(1)
X
(2)
XX
(2)
X
(3)
XX
(2)