Datasheet

219
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
25.4.3 SAMPLE_PRELOAD; $2
Mandatory JTAG instruction for pre-loading the output latches and talking a snap-shot of the input/output pins with-
out affecting the system operation. However, the output latches are not connected to the pins. The Boundary-scan
Chain is selected as Data Register.
The active states are:
• Capture-DR: Data on the external pins are sampled into the Boundary-scan Chain.
• Shift-DR: The Boundary-scan Chain is shifted by the TCK input.
• Update-DR: Data from the Boundary-scan Chain is applied to the output latches. However, the output latches
are not connected to the pins.
25.4.4 AVR_RESET; $C
The AVR specific public JTAG instruction for forcing the AVR device into the Reset mode or releasing the JTAG
Reset source. The TAP controller is not reset by this instruction. The one bit Reset Register is selected as Data
Register. Note that the reset will be active as long as there is a logic 'one' in the Reset Chain. The output from this
chain is not latched.
The active states are:
• Shift-DR: The Reset Register is shifted by the TCK input.
25.4.5 BYPASS; $F
Mandatory JTAG instruction selecting the Bypass Register for Data Register.
The active states are:
• Capture-DR: Loads a logic “0” into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
25.5 Boundary-scan Chain
The Boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well
as the boundary between digital and analog logic for analog circuitry having Off-chip connection.
25.5.1 Scanning the Digital Port Pins
Figure 24-3 shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The cell consists of a
standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a bi-directional pin cell that combines
the three signals Output Control – OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift
Register. The port and pin indexes are not used in the following description.
The Boundary-scan logic is not included in the figures in the datasheet. Figure 24-4 shows a simple digital Port Pin
as described in the section “I/O Ports” on page 50. The Boundary-scan details from Figure 24-3 replaces the
dashed box in Figure 24-4.
When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Register value (but ID
has no synchronizer), Output Data corresponds to the PORT Register, Output Control corresponds to the Data
Direction – DD Register, and the Pull-up Enable – PUExn – corresponds to logic expression PUD
· DDxn ·
PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 24-4 to make the scan chain read the
actual pin value. For Analog function, there is a direct connection from the external pin to the analog circuit, and a
scan chain is inserted on the interface between the digital logic and the analog circuitry.