Datasheet

116
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
PWM). For non-PWM modes the COM2[1:0] bits control whether the output should be set, cleared, or toggled at a
compare match (See “Compare Match Output Unit” on page 123.).
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 128.
18.7.1 Normal Mode
The simplest mode of operation is the Normal mode (WGM2[1:0] = 0). In this mode the counting direction is always
up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-
bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow
Flag (
TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The TOV2 Flag in this case
behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt
that automatically clears the
TOV2 Flag, the timer resolution can be increased by software. There are no special
cases to consider in the normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the output compare to gen-
erate waveforms in normal mode is not recommended, since this will occupy too much of the CPU time.
18.7.2 Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM2[1:0] = 2), the OCR2 Register is used to manipulate the counter
resolution. In CTC mode the counter is cleared to zero when the counter value (TCNT2) matches the OCR2. The
OCR2 defines the top value for the counter, hence also its resolution. This mode allows greater control of the com-
pare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 17-5. The counter value (TCNT2) increases until a com-
pare match occurs between TCNT2 and OCR2, and then counter (TCNT2) is cleared.
Figure 18-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2 Flag. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the
TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done
with care since the CTC mode does not have the double buffering feature. If the new value written to OCR2 is
lower than the current value of TCNT2, the counter will miss the compare match. The counter will then have to
count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC2 output can be set to toggle its logical level on each com-
pare match by setting the Compare Output mode bits to toggle mode (COM2[1:0] = 1). The OC2 value will not be
visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a
TCNTn
OCn
(Toggle)
OCn Interrupt Flag Set
1 4
Period
2 3
(COMn1:0 = 1)