Datasheet

112
ATmega32A [DATASHEET]
Atmel-8155D-AVR-ATmega32A-Datasheet_02/2014
with the Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers
are shared by other timer units.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins,
as detailed later in this section. The asynchronous operation is controlled by the Asynchronous Status Register
(ASSR). The Clock Select logic block controls which clock source the Timer/Counter uses to increment (or decre-
ment) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select
logic is referred to as the timer clock (clk
T2
).
The double buffered Output Compare Register (OCR2) is compared with the Timer/Counter value at all times. The
result of the compare can be used by the waveform generator to generate a PWM or variable frequency output on
the Output Compare Pin (OC2). See “Output Compare Unit” on page 121. for details. The compare match event
will also set the Compare Flag (OCF2) which can be used to generate an output compare interrupt request.
18.2.2 Definitions
Many register and bit references in this document are written in general form. A lower case “n” replaces the
Timer/Counter number, in this case 2. However, when using the register or bit defines in a program, the precise
form must be used (that is, TCNT2 for accessing Timer/Counter2 counter value and so on). The definitions in Table
17-1 are also used extensively throughout the document.
18.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous clock source. The
clock source clk
T2
is by default equal to the MCU clock, clk
I/O
. When the AS2 bit in the ASSR Register is written to
logic one, the clock source is taken from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For
details on asynchronous operation, see “‘ASSR – Asynchronous Status Register” on page 135. For details on clock
sources and prescaler, see “Timer/Counter Prescaler” on page 132.
18.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 17-2 shows a
block diagram of the counter and its surrounding environment.
Figure 18-2. Counter Unit Block Diagram
Signal description (internal signals):
Table 18-1. Definitions
BOTTOM The counter reaches the BOTTOM when it becomes zero (0x00).
MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP The counter reaches the TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be assigned to be the fixed value
0xFF (MAX) or the value stored in the OCR2 Register. The assignment is
dependent on the mode of operation.
DATA BUS
TCNTn Control Logic
count
TOVn
(Int.Req.)
topbottom
direction
clear
TOSC1
T/C
Oscillator
TOSC2
Prescaler
clk
I/O
clk
Tn