Datasheet

97
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock
(clk
T0
). clk
T0
can be generated from an external or internal clock source, selected by the Clock Select bits
(CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be
accessed by the CPU, regardless of whether clk
T0
is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter
Control Register (TCCR0A). There are close connections between how the counter behaves (counts) and how
waveforms are generated on the Output Compare output OC0A. For more details about advanced counting
sequences and waveform generation, see ”Modes of Operation” on page 100.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM01:0 bits.
TOV0 can be used for generating a CPU interrupt.