Datasheet

84
ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET]
8284E–AVR–02/2013
14.3.7 Alternate Functions of Port G
The alternate pin configuration is as follows:
Note: 1. Port G, PG5 is input only. Pull-up is always on.
See Table 28-3 on page 294 for RSTDISBL fuse.
The alternate pin configuration is as follows:
• RESET
– Port G, Bit 5
RESET
: External Reset input. When the RSTDISBL Fuse is programmed (‘0’), PG5 will function as input with pull-
up always on.
• T0/SEG – Port G, Bit 4
T0, Timer/Counter0 Counter Source.
SEG, LCD front plane 32/23.
• T1/SEG24 – Port G, Bit 3
T1, Timer/Counter1 Counter Source.
SEG, LCD front plane 33/24.
Table 14-20. Overriding signals for alternate functions in PF3:PF0.
Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0
PUOE0000
PUOV0000
DDOE 0 0 0 0
DDOV 0 0 0 0
PVOE0000
PVOV0000
PTOE––––
DIEOE 0 0 0 0
DIEOV 0 0 0 0
DI––––
AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT
Table 14-21. Port G pins alternate functions (SEG refers to 100-pin/64-pin pinout).
Port pin Alternate function
PG5 RESET
(1)
PG4 T0/SEG (Timer/Counter0 Clock Input or LCD Front Plane 32/23)
PG3 T1/SEG (Timer/Counter1 Clock Input or LCD Front Plane 33/24)
PG2 SEG (LCD Front Plane 4/4)
PG1 SEG (LCD Front Plane 17/13)
PG0 SEG (LCD Front Plane 18/14)